xr16m581il32 Exar Corporation, xr16m581il32 Datasheet - Page 37

• Manufacturer Part Number: xr16m581il32
• Description: 1.62v To 3.63v Uart With 16-byte Fifo And Vlio Interface
• Manufacturer: Exar Corporation

REV. 1.0.0
These registers make-up the value of the baud rate divisor. The M581 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M581 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See
Baud Rate Generator with Fractional Divisor” on page 11.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[6]: Independent BRG enable
•
•
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0]. .
4.13
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[7]
0
0
1
1
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
DLD[5]
DLD[6]
0
0
1
0
1
1
0
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
T
1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE
ABLE
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
T
ABLE
13: S
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses different BRGs.
Transmitter and Receiver uses same BRG.
Transmitter and Receiver uses same BRG.
14: BRG S
AMPLING
DLD[4]
37
X
Table 13
0
1
R
ATE
ELECT
below and
S
ELECT
BRG
See ”Section 2.7, Programmable
Table 13
S
AMPLING
16X
8X
4X
R
below.
XR16M581
ATE