xr16m2751 Exar Corporation, xr16m2751 Datasheet - Page 9

• Manufacturer Part Number: xr16m2751
• Description: High Performance Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

REV. 1.0.0
The XR16M2751 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide
0x0A for the XR16M2751 and reading the content of DLL will provide the revision of the part; for example, a
reading of 0x01 means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 2751 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode.
Each UART channel in the M2751 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the M2751 offers enhanced feature registers (EMSR,
FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow
control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO
trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in
“Section 3.0, UART INTERNAL REGISTERS” on page
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
2.3
2.4
2.5
2.6
Device Identification and Revision
Channel A and B Selection
Channel A and B Internal Registers
DMA Mode
See Table
CS#
T
T
CSA#
1
0
0
ABLE
ABLE
1
0
1
0
2.
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
1: C
2: C
N/A
A3
0
1
HANNEL
HANNEL
CSB#
1
1
0
0
A
A
AND
AND
9
Channel A selected
Channel B selected
UART de-selected
Channel A and B selected
B S
B S
22.
Channel A selected
Channel B selected
UART de-selected
F
UNCTION
ELECT IN
ELECT IN
F
Table
UNCTION
16 M
68 M
1.
ODE
ODE
XR16M2751