xr16m2651 Exar Corporation, xr16m2651 Datasheet - Page 14

• Manufacturer Part Number: xr16m2651
• Description: High Performance Duart With 32-byte Fifo And Powersave Feature
• Manufacturer: Exar Corporation

XR16M2651
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 32 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. See
The host may fill the transmit FIFO with up to 32 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its selected trigger level. The transmit empty interrupt is enabled by IER
bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty (See
F
F
2.9.1
2.9.2
2.9.3
IGURE
IGURE
6. T
7. T
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
16X or 8X or 4X Clock
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.)
Auto Software Flow Control
Flow Control Characters
( DLD[5:4] )
16X or 8X or 4X
O
O
( DLD[5:4] )
PERATION IN NON
PERATION IN
Clock
Data
Byte
Data Byte
Transmit
Transmit Shift Register (TSR)
FIFO
-FIFO M
AND
Transmit
Register
Holding
(THR)
Transm it Data Shift Register
F
LOW
ODE
(TSR)
Transmit
14
FIFO
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
ODE
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
M
S
B
Figure 7
L
S
B
TXNOFIFO1
below).
TXFIFO 1
Figure 6
below.
REV. 1.0.2