xr16v654 Exar Corporation, xr16v654 Datasheet - Page 11

• Manufacturer Part Number: xr16v654
• Description: 2.25v To 3.6v Quad Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.1
1.0 PRODUCT DESCRIPTION
The XR16V654 (V654) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled and has its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64 bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder
(IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4, and data rate
up to 16 Mbps. The XR16V654 can operate from 2.25 to 3.6 volts. The V654 is fabricated with an advanced
CMOS process.
Enhanced FIFO
The V654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C554, or one byte in the ST16C454. The V654 is designed to work with high performance
data communication systems, that require fast data processing time. Increased performance is realized in the
V654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control
mechanism. This allows the external processor to handle more networking tasks within a given time. For
example, the ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the V654, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Rate
The V654 is capable of operation up to 16 Mbps at 3.3V with 4Xinternal sampling clock rate. The device can
operate at 3.3V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock
source of 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user
can set the prescaler bit and sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the V654 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR
bit-3 can be configured to provide a software controlled or continuous interrupt capability. For backward
compatibility to the ST16C654, the 64-pin LQFP does not have the INTSEL pin. Instead, two different LQFP
packages are offered. The XR16V654DIV operates in the continuous interrupt enable mode by internally
bonding INTSEL to VCC. The XR16V654IV operates in conjunction with MCR bit-3 by internally bonding
INTSEL to GND.
The XR16V654 offers a clock prescaler select pin to allow system/board designers to preset the default baud
rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.
It can then be overridden following initialization by MCR bit-7.
The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
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