xr16l2550im Exar Corporation, xr16l2550im Datasheet - Page 7

• Manufacturer Part Number: xr16l2550im
• Description: Industry Smallest Package Uart With 2.25v To 5.5v Operation
• Manufacturer: Exar Corporation

REV. 1.1.2
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2550 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
.
The L2550 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2550 is
operating at 2.5V, its V
transceiver that is operating at 5V.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The L2550 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2550
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
2.5
CPU Interface
5-Volt Tolerant Inputs
Device Reset
Device Identification and Revision
Channel A and B Selection
Table
F
IGURE
UART_RESET
UART_CSA#
UART_CSB#
UART_INTA
UART_INTB
13). An active high pulse of at least 40 ns duration will be required to activate the reset
RXRDYA#
RXRDYB#
TXRDYA#
TXRDYB#
3.
IOW#
IOR#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
OH
XR16L2550 D
may not be high enough to meet the requirements of the V
ATA
B
US
I
NTERCONNECTIONS
7
CSA#
CSB#
IOR#
IOW#
INTA
INTB
TXRDYA#
RXRDYA#
TXRDYB#
RXRDYB#
RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
LOW VOLTAGE DUART WITH 16-BYTE FIFO
Channel A
Channel B
UART
UART
DSRA#
DTRA#
RTSA#
CTSA#
DTRB#
DSRB#
OP2A#
RTSB#
CTSB#
OP2B#
CDA#
CDB#
GND
RIA#
VCC
TXA
RXA
RIB#
TXB
RXB
VCC
RS-232 Serial Interface
RS-232 Serial Interface
Figure
IH
of a CPU or a serial
3.
XR16L2550