xr17v254 Exar Corporation, xr17v254 Datasheet
xr17v254
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xr17v254 Summary of contents
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... PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT FEBRUARY 2007 GENERAL DESCRIPTION 1 The XR17V254 (V254 single chip 4-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Transmitter) solution, optimized performance and lower power. The V254 device with its fifth generation register set is designed to meet the ...
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... VCC 138 AD31 139 AD30 140 AD29 AD28 141 AD27 142 AD26 143 144 AD25 ORDERING INFORMATION ART UMBER ACKAGE XR17V254IV 144-Lead LQFP XR17V254 PERATING EMPERATURE ANGE -40°C to +85°C 2 REV. 1.0 ENIR 70 69 TMRCK 68 MPIO4 67 MPIO5 66 MPIO6 ...
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... I Initialization device select (active high). Device select to the XR17V254 (active LOW). Device interrupt from XR17V254 (open drain, active LOW). Power Management Event signal. While the Power Management Control/Status Register is set, the V254 asserts the PME# upon receiving a new character or upon change of state of modem inputs on any channel ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN YPE DTR0# 126 O DSR0# 130 CD0# 129 RI0# 128 TX1 106 O RX1 99 RTS1# 104 O CTS1# 100 DTR1# 105 O DSR1# 101 CD1# 102 RI1# 103 TX2 88 O RX2 ...
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... UARTs in the infrared mode. The sampled logic state is transferred to MCR bit [6] in the UART. Power supply for the UART core logic and PCI bus I/O - 3.3V only. The V254 is PCI 3.0 signalling compliant at 3.3V operation. The non-PCI inputs (except XTAL1) are 5V tolerant. This includes all the serial (modem) inputs. 5 XR17V254 ESCRIPTION ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT PIN DESCRIPTIONS AME IN YPE GND 5,20,35,46,63, 89,136 NC 47-54, 71, 72, 75-80, 91-98, 117-124 N : Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. OTE D ESCRIPTION Power supply common, ground. No Connection. These pins are reserved and used by the octal PCI UARTs XR17C158, XR17D158 and XR17V258 ...
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... REV. 1.0.0 FUNCTIONAL DESCRIPTION The XR17V254 (V254) consists of four enhanced 16550 UARTs with a conventional PCI interface and a non- volatile memory interface for PCI plug-and-play auto-configuration. The PCI local bus is a synchronous timing bus where all bus transactions are associated with the bus clock. The V254 supports 66MHz clock and 32-bit wide read and write data transfer operations including data burst mode through the PCI interface ...
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... PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 1.0 XR17V254 INTERNAL REGISTERS The XR17V254 UART has three different sets of registers as shown in Configuration Space Registers are for plug-and-play auto-configuration when connecting the device to a the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification ...
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... RO Unimplemented Base Address Register (returns zeros) 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x20 31:0 RO Unimplemented Base Address Register (returns zeros OCAL US ONFIGURATION PACE D ESCRIPTION 9 XR17V254 EGISTERS R V ESET ALUE ( ) HEX OR BINARY 0x0254 0x13A8 0b 0b 00b 0b 00b 0000b ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x24 31:0 RO Unimplemented Base Address Register (returns zeros) 0x28 31:0 RO Reserved 0x2C 31:16 EWR Subsystem ID (write from external EEPROM by customer) 15:0 EWR Subsystem Vendor ID (write from external EEPROM by cus- ...
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... D0 S TATE The XR17V254 must be placed in the D0 state before being used in a system. The D0 state represents two states - D0 Uninitalized and D0 Active. Upon entering D0 from power up or transition from the D0 Uninitialized state. Once initialized by the system software, the V254 will enter the D0 Active state. ...
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... Management Registers. This register can be used to store application-specific information which may be used by the device driver to initialize the device appropriately DDRESS FFSET ITS YPE 0x48 31:0 EWR N : EWR=Read/Write from external EEPROM. OTE XR17V254 D0 Uninitialized VCC Removed D3 hot ABLE PECIAL EAD RITE EGISTER D ESCRIPTION ...
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... EFINITIONS V254’ PCI C S ONFIGURATION S A [D15:D0] PACE DDRESS ATA (WORD O FFSET 0x00 0x02 0x08 * 0x0A 0x2C 0x2E 0x48 0x4A Table 5 below. Every time a read or write operation is 13 XR17V254 D V EFAULT ALUES ) 0x13A8 0x0254 0x0200 0x0700 0x0000 0x0000 0x0000 0x0000 . ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT T 5: XR17V254 UART ABLE FFSET DDRESS EMORY PACE 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved 0x080 - 0x093 DEVICE CONFIGURA- TION REGISTERS 0x094 - 0x0FF Reserved 0x100 UART 0 – Read FIFO 0x100 UART 0 – ...
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... Read-only Device revision Read-only Device identification Write-only Read/Write MPIO interrupt mask Read/Write MPIO level control Read/Write MPIO output control Read/Write MPIO input polarity select Read/Write MPIO select 15 XR17V254 BYTE ALIGNMENT RESET STATE Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 Bits [7:0] = 0x00 ...
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... The Global Interrupt Register The XR17V254 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme is an 8-bit indicator representing all 4 channels with each bit representing each channel from This permits the interrupt routine to quickly vector and serve that UART channel and determine the source(s) in each individual routines ...
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... MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected Reserved. MPIO pin(s). Available only within channel 0, reserved in other channels. TIMER Time-out. Available only within channel 0, reserved in other channels. 9: UART C [3:0] I HANNEL NTERRUPT 17 XR17V254 . The Timer and MPIO interrupts are for INT1 Register Channel-1 Channel-0 Bit Bit Bit Bit ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 1.6.2 General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL XX-XX-00-00 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal crystal oscillator or externally on pin TMRCK. The timer can be set single-shot for a one-time event or re-triggerable for a periodic signal ...
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... Timer has been started: Any write to TIMER MSB, LSB registers ■ Issue of any command other than ’Start Timer’, ’Stop Timer’ and ’Reset Timer’ ■ 10: TIMER CONTROL R ABLE EGISTERS Figure the Timer times out, re-starting the 19 XR17V254 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT Timer Operation in Re-triggerable Mode: In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the terminal count clocks) and toggle LOW and stay LOW for a similar amount of time (Q clocks). The above step will keep repeating until the Timer is stopped at which time the output will become HIGH (default state) ...
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... Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 Table 21 for details. bit [0] =1 resets UART channel 0 with bit RESET Register Individual UART Channel Reset Enable Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0 21 XR17V254 M ODES Timer Timed TIMERCNTL Timer Timed Out read Out ...
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... DVID register provides device identification. A return value of 0x44 from this register indicates the device is a XR17V254. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes ...
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... General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-00)” on page 18 1.6.10 MPIO REGISTER Bit [7] represents MPIO7 pin and bit [0] represents MPIO0 pin. There are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. . Figure 9 shows the internal circuitry. 23 XR17V254 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT IGURE ULTIPURPOSE INPUT MPIOINT [7:0] INT AND MPIOLVL [7:0] Read Input Level MPIOINV [7:0] (Input Inversion Enable =1) MPIOLVL [7:0] (Output Level) MPIO3T [7:0] (3-state Enable =1) MPIOSEL [7:0] (Select Input=1, Output=0 ) MPIOINT [7:0] (default 0x00) Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit [0] enables input pin 0 for interrupt, and bit [7] enables input pin 7 ...
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... MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOINV Register Multipurpose Input Signal Inversion Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 MPIOSEL Register Multipurpose Input/Output Selection MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 25 XR17V254 page 29 for programming details. ...
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... FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT The XR17V254 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/ ...
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... Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780 The XR17V254 also provides the same RX FIFO data along with the LSR status information of each byte side- by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2) and 0x780 (channel 3). The entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD reads ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 3.1.3 Tx FIFO Data Loading at locations 0x100, 0x300, 0x500, 0x700 The TX FIFO data (up to the maximum 64 bytes) can be loaded in a single burst 32-bit write operation (maximum 16 DWORD writes) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500 (channel 2) and 0x700 (channel 3) ...
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... In the formulas above, please note that: TRUNC (N) = Integer Part of N. For example, TRUNC (5. ROUND ( rounded towards the closest integer. For example, ROUND (7. and ROUND (9.9) = 10. DLM = TRUNC( Required Divisor) >> 8 DLL = TRUNC (Required Divisor) & 0xFF 29 XR17V254 16 - 0.0625) in increments of 0.0625 (1/ Table 12 shows the Table 12 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 11 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer T 12: T ABLE YPICAL DATA RATES WITH EQUIRED IVISOR FOR O D 16x Clock O UTPUT ATA R (Decimal) ATE 400 3750 2400 ...
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... Z CRYSTAL OR EXTERNAL CLOCK AT D IVISOR DLM P DLL P ROGRAM BTAINABLE IN V (HEX) V ALUE ALUE V254 3 12/ 4/ 10/ 8/16 0 Figure 12 below explains how it works. 31 XR17V254 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX)) R (%) ALUE ATE 0. ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 12. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 RXA FIFO ...
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... Receive IR Pulse (RX pin) RX Data RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 33 XR17V254 ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 4.4 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit [4] to logic 1. All regular UART functions operate normally. Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Write-only Read-only Write-only Read/Write E R NHANCED EGISTER Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Read-only Write-only Read-only Write-only Read-only 35 XR17V254 C OMMENTS LCR[ LCR[ LCR[ LCR[ LCR[ LCR[ Xon,Xoff Rcvd. Flags ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT T 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE EAD A B [7] DDRESS AME RITE A3- RHR R BIT [ THR W BIT [ DLL R/W BIT [ DLM R/W BIT [ ...
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... XON2 W Bit [ MCR bits [3:2] (OP1 and OP2 outputs) are not available in the XR17V254. They are present for 16C550 OTE compatibility during Internal loopback, see 4.6 Transmitter The transmitter section comprises bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR) ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 15 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (8XMODE Register) Transmit Shift Register (TSR) 4.6.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit [5]) is set whenever the FIFO is empty ...
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... ECEIVER PERATION IN NON 16X or 8X Clock (8XMODE Register) Error Receive Flags in Data Byte LSR bits and Errors 4:2 -FIFO M ODE Receive Data Shift Data Bit Register (RSR) Validation Receive Data RHR Interrupt (ISR bit-2) Holding Register (RHR) 39 XR17V254 Receive Data Characters RXFIFO1 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 4.7.2 Receiver Operation with FIFO F 18 IGURE ECEIVER PERATION IN 16X or 8X Sampling Clock (8XMODE Reg.) Receive Data Shift Register (RSR) 64 bytes by 11- bit wide FIFO Receive Data Receive Data Byte and Errors 5 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR17V254 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT IER[1]: TX Ready Interrupt Enable In non-FIFO mode interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and again when the TX FIFO becomes empty ...
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... MSR (Modem Status Register RXRDY (Received Xon/Xoff or Special character CTS#/DSR#, RTS#/DTR# change of state None (default) and “Section 5.5.2, Interrupt Clearing:” on page 42 below shows the selections. 43 XR17V254 L EVEL S OURCE OF THE INTERRUPT Table 15 ). See “Section for details. ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device provided for legacy software compatibility. • Logic 0 = Set DMA to mode 0 (default). • ...
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... Programmable via RXTRG register 45 XR17V254 L S EVEL ELECTION T RANSMIT T C RIGGER OMPATIBILITY L EVEL 1 (default) 16C550, 16C2550, 16C2552, 16C554, 16C580, 16L580 16 16C650A, 16L651 16C654 Programmable 16L2752, 16L2750, ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR bit [5] selects the forced parity format. • LCR bit [5] = logic 0, parity is not forced (default). • LCR bit [5] = logic 1 and LCR bit [4] = logic 0, parity bit is forced to a logical 1for the transmit and receive data. • ...
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... Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. MCR[4]: Internal Loopback Enable • Logic 1 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and BIT [0] W ORD LENGTH 0 5 (default Figure XR17V254 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode) This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to set ’ ...
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... MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit [3] in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 49 XR17V254 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit [2] in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. ...
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... ELAY XR17V254 RANSMIT TO ECEIVE ATA IT S IME ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT MSR [2]: Receiver Disable (requires EFR bit [4]=1) This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate in one of the following ways character is being received at the time of setting this bit, that character will be correctly received. No ■ ...
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... Table 20 ). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 53 XR17V254 Table ABLE IS ELECTED ( ) YSTERESIS CHARACTERS 0 +/- 4 +/- 6 +/- 8 +/- 8 +/- 16 +/- 24 +/- 32 +/- 12 +/- 20 +/- 28 +/- 36 +/- 40 +/- 44 +/- 48 +/- 52 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT EFR[6]: Auto RTS or DTR Flow Control Enable RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/ DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 55 XR17V254 Table ECEIVE OFTWARE LOW ONTROL ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT 5.20 XCHAR REGISTER, READ ONLY This register gives the status of the last sent control character (Xon or Xoff) and the last received control character (Xon or Xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled. ...
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... Bits [7:0] = 0x00 RFTRG Bits [7:0] = 0x00 XCHAR Bits [7:0] = 0x00 XON1 Bits [7:0] = 0x00 XON2 Bits [7:0] = 0x00 XOFF1 Bits [7:0] = 0x00 XOFF2 Bits [7:0] = 0x00 T 21: UART RESET CONDITIONS ABLE I/O SIGNALS TX[ch-3:0] IRTX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] EECK EECS EEDI 57 XR17V254 RESET STATE HIGH LOW HIGH HIGH LOW LOW LOW ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (20x20x1.4mm 144-LQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING O O TA=-40 + INDUSTRIAL GRADE S P YMBOL ...
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... XR17V254 U N NITS OTES MHz On-chip osc. MHz 0.3VCC out 0.7VCC out 0.6VCC out 0.18VCC out VCC+4 > Vin ≥ VCC < Vin ≤ -1 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 19. PCI B C IGURE US ONFIGURATION CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target CLK Host FRAME# Host AD[31:0] Host Target C/BE[3:0]# Host IRDY# Host TRDY# Target DEVSEL# Target ...
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... Note: PERR# and SERR are optional in a bus target application. Even Parity is on AD[31:0], C/BE[3:0]#, and PAR UART EGISTERS EAD PERATION FOR Data BYTE Byte Enable# = DWORD Data Parity Active Active 61 XR17V254 B DWORD YTE Data WORD Data Parity Active PCI_RD1 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 21 IGURE EVICE ONFIGURATION REGISTERS TION CLK Host FRAME# Host Data AD[31:0] Address DWORD DWORD Host Target Bus C/BE[3:0]# Byte Enable# = DWORD CMD Host IRDY# Host TRDY# Target DEVSEL# Target Address ...
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... Note: PERR# and SERR are optional in a bus target application. Even Parity is on AD[31:0], C/BE[3:0]#, and PAR R , UART R R EGISTERS EGISTERS AND 8 13 Data Data Data Data Active Active 63 XR17V254 ECEIVE ATA URST EAD PERATION 18 23 Data Data Data Data Active ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT F 23. 3.3V PCI B C IGURE US LOCK 0.5VCC CLK 0.4VCC 0.3VCC T_val Output Delay T_on Tri-State Output Input (DC 66MH ) TO Z T_cyc T_low T_high Measurement Condition Parameters Vth = 0.6VCC Vtl = 0.2VCC V_trise Vtest = 0.4VCC Vtrise = 0 ...
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... Trigger Level Trigger Level BAUD RATE CLOCK of 16X RIGGER EVEL DATA BITS (5- De-asserted at below trigger level 65 XR17V254 STOP BIT D7 PARITY NEXT BIT DATA START BIT TXNOFIFO-1 STOP BIT D7 First byte that PARITY BIT reaches the trigger level ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT PACKAGE DIMENSIONS 108 109 144 Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL α 144 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) ...
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... Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. D ESCRIPTION Advanced Datasheet Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" consistent with JEDEC and Industry norms. Preliminary Datasheet. Final Datasheet. NOTICE 67 XR17V254 ...
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... UT OF THE EVICE ................................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ......................................................................................................... 3 FUNCTIONAL DESCRIPTION .......................................................................................... 7 PCI Local Bus Interface .............................................................................................................................................. 7 PCI Local Bus Configuration Space Registers ........................................................................................................... 7 Power Management Registers ................................................................................................................................... 7 EEPROM Interface ..................................................................................................................................................... 7 1.0 XR17V254 INTERNAL REGISTERS........................................................................................................ XR17V254 R S IGURE HE EGISTER 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... PCI L ...
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... AND LOW ONTROL ODE L ..................................................................................................................... 43 EVEL .......................................................................... 45 RIGGER ABLE AND EVEL ELECTION IRECTION ONTROL ELAY FROM RANSMIT EVELS HEN RIGGER ABLE IS ELECTED F ........................................................................................................................ 55 UNCTIONS 3.3V ................................................................. 58 FOR SIGNALLING II XR17V254 .......................................................... 28 ................................................. 30 AMPLING EFR B -4. ....... ................................................. 51 TO ECEIVE ................................................................ 53 ...
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... XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT TA=-40o to +85oC (industrial grade) Supply Voltage, VCC = 3.0 - 3.6V.................................................................. 58 AC ELECTRICAL CHARACTERISTICS TA=-40o to+85oC (industrial grade) VCC = 3.0 - 3.6V............................................................................................. 59 F 19. PCI B C IGURE US ONFIGURATION F 20 IGURE EVICE ONFIGURATION AND F 21 IGURE EVICE ONFIGURATION REGISTERS F 22 ...