xr21b1411 Exar Corporation, xr21b1411 Datasheet - Page 23

• Manufacturer Part Number: xr21b1411
• Description: Enhanced 1-ch Full-speed Usb Uart
• Manufacturer: Exar Corporation

REV. 1.1.0
OTP registers are incrementally "One Time Programmable", i.e. various portions of the memory at the bit level
can be programmed at different times. Note that all register reset default values are ’0’ indicating that these
bits have not been programmed. Conversely a ’1’ in any bit position indicates that bit has been previously
programmed. Some OTP bits will be pre-programmed at the factory before shipments to customers.
OTP_CONFIG0[0]: Reserved
OTP_CONFIG0[1]: Lowpower_Polarity
OTP_CONFIG0[7:2]: Reserved
OTP_CONFIG1[7:0]: Reserved
OTP_CONFIG2[7:0]: Reserved
OTP_CONFIG3[2:0]: Core_Clock_Select
The B1411 core can run at a fraction of the 48 MHz bus clock to minimize power consumption in the core.
Refer to
4x the maximum baud rate setting desired in a customer application.
OTP_CONFIG3[3]: Enable_VBUS_Sense
OTP_CONFIG3[7:4]: Reserved
3.2.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
Factory programmed - overwriting this bit may cause functional damage to the B1411 device
Sets the polarity of the LOWPOWER output pin
Factory programmed - overwriting these bits may cause functional damage to the B1411 device
Factory programmed - overwriting these bits may cause functional damage to the B1411 device
Factory programmed - overwriting these bits may cause functional damage to the B1411 device
Controls whether VBUS is sensed.
Logic 0 = LOWPOWER output pin will be active low
Logic 1 = LOWPOWER output pin will be active high
Logic 0 = VBUS sense is not enabled (typically used in bus-powered mode)
Logic 1 = VBUS sense is enabled (typically used in self-powered mode)
Table 12
OTP Memory Descriptions
OTP Config0 (Read / Write OTP)
OTP Config1 (Read / Write OTP)
OTP Config2 (Read / Write OTP)
OTP Config3 (Read / Write OTP)
3'b100 -
3'b000
3'b001
3'b010
3'b011
V
3'b111
ALUE
for core clock divider settings. Note that the selected core clock rate must be a minimum of
DIV_BY_1
DIV_BY_2
DIV_BY_4
DIV_BY_8
Not Used
N
AME
T
Core Clock = CLOCK / 1 (48 MHz)
Core Clock = CLOCK / 2 (24 MHz)
Core Clock = CLOCK / 4 (12 MHz)
Core Clock = CLOCK / 8 (6 MHz)
Reserved - Using these settings may cause functional dam-
age to the B1411 device
ABLE
12: C
ORE
23
C
LOCK
D
D
ENHANCED 1-CH FULL-SPEED USB UART
ESCRIPTION
IVIDER
XR21B1411