xr20m1280 Exar Corporation, xr20m1280 Datasheet - Page 43

• Manufacturer Part Number: xr20m1280
• Description: I2c/spi Uart With 128-byte Fifo And Integrated Level Shifters
• Manufacturer: Exar Corporation

REV. P1.1.1
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
This register provides the current state of the GPIO pins.
If a GPIO has been configured as an input:
If a GPIO has been configured as an output:
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[2]: Send TX Immediately
•
•
EMSR[3]: Invert RTS in RS485 mode
•
•
3.12
3.13
3.14
Logic 0 = Do not send TX immediately (default).
Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the
TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only
1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If
more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
■
■
■
■
A read will report the current state of the input.
A write to any GPIO configured as an input will not have any effect.
A read will report the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
A write will change the current value of the register. The current value of the register will also be the
current state of the output pin if three-state mode is not enabled (GPIO3T register).
Scratch Pad Register (SPR) - Read/Write
GPIO Level Register (GPIOLVL) - Read/Write
Enhanced Mode Select Register (EMSR) - Write-only
FCTR[6] EMSR[1] EMSR[0] Scratchpad is
0
1
1
1
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
X
X
0
1
T
ABLE
16: S
X
0
1
1
CRATCHPAD
PRELIMINARY
Scratchpad
RX FIFO Level Counter Mode
TX FIFO Level Counter Mode
Alternate RX/TX FIFO Counter Mode
43
S
WAP
S
ELECTION
XR20M1280