xr20v2170 Exar Corporation, xr20v2170 Datasheet
xr20v2170
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xr20v2170 Summary of contents
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... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Battery-Operated Devices • Cellular Data Devices • Factory Automation and Process Controls F 1. XR20V2170 B D IGURE LOCK IAGRAM rfa ...
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... I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER IGURE IN UT SSIGNMENT N.C. N.C. N.C. VREF VCC A0/CS# A1/ ORDERING INFORMATION P N ART UMBER XR20V2170IL40 40-pin QFN 40-Pin QFN ...
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... If SPI configuration is selected, this pin is the SPI data input pin. SPI data output pin. If SPI configuration is selected then this pin is a three-state- 2 able output pin C-bus configuration is selected, this pin is undefined and must be left unconnected. 3 XR20V2170 2 C-bus configuration is 2 C-bus onfiguration is ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER Pin Description 40-QFN N T AME YPE MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels RXD 10 O TXD 11 O RTS 12 I/O DTR 1 I/O DSR 4 I CTS Ancillary signals (CMOS/TTL Voltage Levels) ...
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... Additionally, the V2170 includes the ACP pin which the user can shut down the charge pump for the RS-232 drivers when the V2170 is already in sleep mode. The Power-Save feature further isolates the databus interface to further reduce power consumption in the sleep mode. The XR20V2170 is a 2.97V to 3.63V device. The V2170 is fabricated with an advanced CMOS process. ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The V2170 can operate with either an I the I2C/SPI# input pin. The V2170 can operate with either an I interface is selected via the I2C/SPI# input pin. 2 2.1.1 I C-bus Interface ...
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... Data transferred (n bytes + acknowledge) DATA A DATA NA acknowledge Not acknowledge Data transferred (n bytes + acknowledge) SLAVE DATA A Sr ADDRESS Read or acknowledge Repeated write START condition Direction of transfer may change at this point 7 XR20V2170 P STOP condition P STOP condition Data transferred (n bytes + acknowledge) R/W A DATA A P acknowledge acknowledge STOP condition ...
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... UART Internal Register Address A3:A0 2:1 UART Channel Select ’00’ = UART Channel A, other values are reserved 0 Reserved After the last read or write transaction, the I 2 C-bus. To distinguish itself from the other devices on the XR20V2170 ABLE DDRESS DDRESS VCC ...
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... PERATION FOR RANSMITTER FCR FCR B (FIFO D ) ISABLED HIGH = FIFO above trigger level LOW = FIFO below trigger level or FIFO empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or transmitter empty 9 XR20V2170 Table 3 below. Table (FIFO NABLED ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER T ABLE FCR (FIFO D ISABLED IRQ# Pin HIGH = no data LOW = 1 byte 2.6 Crystal Oscillator or External Clock Input The V2170 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device ...
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... DLL = TRUNC(Required Divisor) & 0xFF DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 Fractional Baud Rate Generator Logic Prescaler Divide by 4 MCR Bit-7=1 11 XR20V2170 Table 6 shows the Table sampling rate, these 16X Sampling Rate Clock to Transmitter and Receiver ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 150 19200 78.125 25000 60 28800 52.0833 38400 39.0625 ...
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... Transmit Shift Register (TSR FIFO AND LOW ONTROL ODE Transmit THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transmit Data Shift Register (TSR) 13 XR20V2170 TXNOFIFO1 TXFIFO 1 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 2.9 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate ...
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... RHR Interrupt (ISR bit-2) programmed for Trigger=16 desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to RTS# de-asserts when data fills to the Halt Level Halt Level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data Figure 13): 13): 15 XR20V2170 M ODE Receive Data Characters RXFIFO1 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. F 13. A RTS CTS F IGURE UTO AND LOW Local UART UARTA ...
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... DLM and DLL registers is a non-zero value ■ ■ sleep mode is enabled (IER bit modem inputs are not toggling (MSR bits 0 ■ RXD input pin is idling LOW ■ I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER (See Table 15), the V2170 compares one or two sequential receive data 17 XR20V2170 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER The V2170 UART portion stops its crystal oscillator to conserve power in this mode. The user can check the XTAL2 pin for no clock output as an indication that the device has entered the partial sleep mode. ...
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... F 14 IGURE NTERNAL OOP I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER B ACK VCC Transmit Shift Register (THR/FIFO) MCR bit-4=1 Receive Shift Register (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD# 19 XR20V2170 TX RX RTS# CTS# DTR# DSR# RI# CD# ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 3.0 UART INTERNAL REGISTERS The complete register set is shown below UART INTERNAL REGISTER ADDRESSES ABLE A DDRESS 0X00 RHR - Receive Holding Register THR - Transmit Holding Register 0X00 DLL - Divisor LSB 0X01 DLM - Divisor MSB ...
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... Bit-3 Resume Resume Halt Bit-2 Bit-1 Bit-0 Bit-3 RX Trig RX Trig TX Trig Bit-2 Bit-1 Bit-0 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 21 XR20V2170 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX Data Stat ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x0A IODir RD/WR 0 0x0B IOState RD/WR 0 0x0C IOIntEna RD/WR 0 0x0D reserved - 0 0x0E IOControl RD/WR 0 0x0F EFCR RD/WR 0 0x00 DLL RD/WR Bit-7 0x01 DLM RD/WR Bit-7 0x02 DLD ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR20V2170 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER IER[4]: Sleep Mode Enable (requires EFR bit • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • ...
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... RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register GPIO (General Purpose Inputs RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 25 XR20V2170 L EVEL S OURCE OF INTERRUPT Table 9). ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered) ...
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... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER BIT-0 W ORD LENGTH (default TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7 1-1/2 6,7,8 2 (default) 27 XR20V2170 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • ...
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... EGISTER AT DDRESS FFSET X Modem Status Register (MSR) 0 Modem Status Register (MSR) 1 Trigger Control Register (TCR) 13 EGISTER AT DDRESS FFSET X Scratchpad Register (SPR) 0 Scratchpad Register (SPR) 1 Trigger Level Register (TLR) Figure 29 XR20V2170 14. ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. LSR[0]: Receive Data Ready Indicator • Logic data in receive holding register or FIFO (default). ...
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... Transmission Control Register (TCR) - Read/Write (requires EFR bit This register replaces MSR and is accessible only when MCR[ This 8-bit register is used to store the RX FIFO threshold levels to halt/resume transmission during hardware or software flow control. I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 31 XR20V2170 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER TCR[3:0]: RX FIFO Halt Level A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used ...
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... IOState register keeps the logic value that generated the interrupt. 4.19 Extra Features Control Register (EFCR) - Read/Write EFCR[7:3]: Reserved These bits are reserved and should be left at "0000". I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 33 XR20V2170 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER EFCR[2]: Transmitter Disable UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state. ...
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... Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 35 XR20V2170 ECEIVE OFTWARE LOW ONTROL ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts HIGH at the programmed HALT level ...
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... Bits 7-4 = Logic levels of the inputs inverted [1] Bits 7-0 = 0xFF Bits 7-0 = 0x0F Bits 7-0 = 0x00 Bits 7-0 = 0x40 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 [1] Bits 7-0 = 0x00 RESET STATE HIGH HIGH HIGH HIGH HIGH 37 XR20V2170 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (40-QFN) 4 Volts GND-0. - -65 ...
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... TA=+25C 0 ohm TA=+25C ± ± ohm load on all transmitter outputs 5.0 6.5 300 ohm Vcc=0V, transmitter output=+/-2V ± 250 Kbps R =3Kohm, CL=1000pF 50pF to 2500pF, RL=3-7Kohm L 39 XR20V2170 C ONDITIONS =+25C, no load A =+25C, no load A =+25C, no load A =+25C, no load, all A , ACP) ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER AC ELECTRICAL CHARACTERISTICS - UART CLOCK o Unless otherwise noted: TA=-40 to +85 S YMBOL XTAL1 UART Crystal Oscillator ECLK UART External Clock T External Clock Time Period ECLK F 15 IGURE LOCK IMING VIHCK External Clock VILCK o C, Vcc=2.97 - 3.63V ...
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... C-bus transmit interrupt clear D8 T SCL delay after reset D15 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER o C, Vcc=2.97 - 3.63V S TANDARD ARAMETER M 4.7 4.0 4.7 250 4.7 4.0 0.5 0.2 0.2 0.2 0.2 0.2 0.2 0.2 1.0 41 XR20V2170 ODE AST ODE I2C-B I2C NIT 100 0 400 kHz µ s 1.3 µ s 0.6 µ ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 16. SCL IGURE ELAY FTER ESET RESET# SCL 2 F 17 IGURE US IMING IAGRAM START Protocol condition ( SU;STA LOW SCL T T BUF SDA T HD;STA F 18 IGURE RITE O UTPUT SLAVE ...
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... SDA W A ADDRESS IRQ# GPIOn I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER SLAVE A MSR REGISTER A S ADDRESS ACK from slave SLAVE IOSTATE REG ADDRESS XR20V2170 R A DATA ACK from slave ACK from master R A DATA ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 21 IGURE ECEIVE NTERRUPT Start bit RX D0 IRQ IGURE ECEIVE NTERRUPT LEAR SLAVE SDA W A ADDRESS IRQ IGURE RANSMIT NTERRUPT SLAVE SDA W ADDRESS IRQ SLAVE ...
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... I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER o C, Vcc=1.62 - 3.63V M ARAMETER 100 20 100 20 250 100 100 200 200 200 200 200 200 200 ... ... ... ... 45 XR20V2170 NIT ONDITIONS 100 100 100 100 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 25. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R GPIOx F 26. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R DTR# (GPIO5) S UTPUT WITCH A0 CH1 CH0 UTPUT WITCH ...
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... SCLK SI R GPIOx IRQ# F 28. R MSR C M IGURE EAD TO LEAR CS# SCLK SI R IRQ# I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER TX INT A0 CH1 CH0 INT ODEM A0 CH1 CH0 D12 47 XR20V2170 td11 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER F 29. R IOS C IGURE EAD TATE TO LEAR CS# SCLK SI R IRQ# F 30. R RHR C RX INT IGURE EAD TO LEAR CS# SCLK SI R IRQ# GPIO INT A0 CH1 CH0 D13 A0 CH1 CH0 ...
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... Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.232 0.240 5.90 0.189 0.197 4.80 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.014 0.018 0.35 0.008 - 0.20 49 XR20V2170 MAX 1.00 0.05 0.25 6.10 5.00 0.30 0.45 - ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REVISION HISTORY D R ATE EVISION October 2006 P1.0.0 Preliminary Datasheet. December 2006 P1.0.1 Updated Package Drawing and Diagrams. Added I2C/SPI timing diagrams. January 2007 P1.0.2 Corrected pinout and pin descriptions on pages 2-4. June 2007 1.0.0 Final Datasheet. Corrected IEC spec # on page 1. ...
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... O LAVE IGURE ASTER EADS ROM LAVE F 6. I2C D F ........................................................................................................................................................ 7 IGURE ATA ORMATS 2.2 I2C-BUS ADDRESSING ...................................................................................................................................... XR20V2170 I2C A M ABLE DDRESS T 2: I2C S -A ............................................................................................................................................................ 8 ABLE UB DDRESS 2.2.1 SPI BUS INTERFACE ..................................................................................................................................................... SPI .................................................................................................................................................. 9 ABLE IRST YTE ORMAT 2.3 DEVICE RESET ................................................................................................................................................... 9 2 ...
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... XR20V2170 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 23 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 23 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 24 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 24 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 25 ...