xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 12

• Manufacturer Part Number: xr20v2172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X
internal clock. A bit time is 16 (8 if 8X or 4 if 4X) clock periods (see DLD[5:4]). The transmitter sends the start-
bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The
status of the FIFO and TSR are reported in the Line Status Register (LSR[6:5]).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.8
2.8.1
Output Data
Required
100000
115200
153600
200000
225000
230400
250000
10000
19200
25000
28800
38400
50000
57600
75000
Rate
2400
4800
9600
400
Transmitter
T
ABLE
Transmit Holding Register (THR) - Write Only
6: T
YPICAL DATA RATES WITH A
D
16x Clock
(Decimal)
IVISOR FOR
52.0833
39.0625
26.0417
13.0208
156.25
78.125
9.7656
6.6667
6.5104
312.5
3750
625
150
7.5
60
30
20
15
6
O
BTAINABLE IN
312 8/16
156 4/16
78 2/16
52 1/16
39 1/16
26 1/16
D
9 12/16
6 11/16
7 8/16
6 8/16
V2172
3750
IVISOR
625
150
60
30
20
15
13
6
24 MH
DLM P
V
ALUE
Z CRYSTAL OR EXTERNAL CLOCK AT
12
ROGRAM
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(HEX)
DLL P
V
ALUE
A6
9C
4E
3C
1E
1A
71
38
96
34
27
14
ROGRAM
D
F
9
7
6
6
6
(HEX)
DLD P
V
ALUE
16X S
C
ROGRAM
0
0
8
4
0
2
0
1
1
0
1
0
0
0
8
B
8
0
(HEX)
AMPLING
D
ATA
R
ATE
REV. 1.0.0
0.04
0.08
0.16
0.16
0.31
0.16
E
0
0
0
0
0
0
0
0
0
0
0
0
0
RROR
(%)