71m6521fe Maxim Integrated Products, Inc., 71m6521fe Datasheet - Page 43

• Manufacturer Part Number: 71m6521fe
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

Three-Wire EEPROM Interface
A 500kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is selected with
DIO_EEX=3. The same 2-wire EECTRL register is used, except the bits are reconfigured, as shown in Table 58. When EECTRL
is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of
the EECTRL bits.
The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All commands begin when
the EECTRL register is written. Transactions start by first raising the DIO pin that is connected to CS. Multiple 8-bit or less
commands such as those shown in Figure 9 through Figure 13 are then sent via EECTRL and EEDATA. When the transaction
is finished, CS must be lowered. At the end of a Read transaction, the EEPROM will be driving SDATA, but will transition to
HiZ (high impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0 and HiZ=0 to
take control of SDATA and force it to a low-Z state.
v1.0
Control
3-0
Bit
7
6
5
4
SDATA output Z
SDATA (output)
CNT[3:0]
EECTRL Byte Written
Name
SCLK (output)
BUSY
WFR
HiZ
RD
Write -- No HiZ
BUSY (bit)
Read/Write
W
W
W
W
R
Figure 9: 3-Wire Interface. Write Command, HiZ=0.
© 2005-2008 TERIDIAN Semiconductor Corporation
Table 58: EECTRL bits for 3-wire interface
D7
Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed
until a rising edge is seen on the data line. This bit can be used during
the last byte of a Write command to cause the INT5 interrupt to occur
when the EEPROM has finished its internal write sequence. This bit is
ignored if HiZ=0.
Asserted while serial data bus is busy. When the BUSY bit falls, an INT5
interrupt occurs.
Indicates that the SD signal is to be floated to high impedance immedi-
ately after the last SCK rising edge.
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be sent
MSB first to EEPROM, shifted out of EEDATA’s MSB. If CNT is zero,
SDATA will simply obey the HiZ bit.
D6
CNT Cycles (6 shown)
(LoZ)
D5
71M6521DE/71M6521FE
D4
D3
Energy Meter IC
D2
INT5
DATASHEET
JANUARY 2008
Page: 43 of 101