isppac-clk5620v-01t48c Lattice Semiconductor Corp., isppac-clk5620v-01t48c Datasheet - Page 16

• Manufacturer Part Number: isppac-clk5620v-01t48c
• Description: In-system Programmable, Zero-delay Clock Generator With Universal Fan-out Buffer
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 2. PAC-Designer Recommended Loop Filter Settings
Note that the choice of loop filter parameters can have significant effects on settling time, output jitter, and whether
the PLL will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2
were chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that
when the skew mode is set to ‘coarse’, the effective value of NxV must be considered to have doubled. Refer to the
section titled ‘Coarse Skew Mode’ on page 28 for further details.
The PLL’s loop bandwidth is a function of both the divider configuration and the loop filter settings. Figure 12 shows
the loop bandwidth as a function of the total feedback division ratio (N x V
in this plot, the PLL loop filter was set to the corresponding value recommended in Table 2. The use of non-recom-
mended loop filter settings may result in significantly different bandwidths for a given NxV divider setting.
Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (nominal)
VCO
The ispClock5600 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz.
The VCO is implemented using differential circuit design techniques which minimize the influence of power supply
noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period.
Using the VCO as the basis for controlling output skew allows for highly precise and consistent skew generation,
both from device-to-device, as well as channel-to-channel within the same device.
1.75
1.25
0.75
0.25
N x V
12 to 14
18 to 20
24 to 26
32 to 64
1.5
0.5
2 to 8
0
1
2
10
16
22
28
30
0
*loop filter configured to recommended setting
FBK
Feedback Divider Setting* (Typical)
N x V Feedback Division Product
PLL Loop Bandwidth vs.
16
I (µA)
16
11
13
15
17
19
21
22
5
7
9
32
48
R (k )
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
ispClock5600 Family Data Sheet
FBK
). For each NxV feedback divider point
64