lfxp20c-5f388c Lattice Semiconductor Corp., lfxp20c-5f388c Datasheet
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LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Introduction The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/ single architecture that is both non-volatile and infinitely reconfigurable to support cost-effective system designs. The re-programmable non-volatile technology used in ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Figure 2-1. LatticeXP Top Level Block Diagram Programmable I/O Cell (PIC) includes sysIO Interface Non-volatile Memory sysCONFIG Programming Port (includes dedicated and dual use pins) Programmable Functional Unit (PFU) PFU and PFF Blocks The core of the LatticeXP ...
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Lattice Semiconductor Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 ...
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Lattice Semiconductor Table 2-1. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose Input Multi-purpose Input Control signal Input Control signal Input Control signal Input Inter-PFU signal Output Data signals Output Data signals Output Data signals ...
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Lattice Semiconductor The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number ...
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Lattice Semiconductor Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT MUX 8x1 x 2 LUT 7x1 or MUX 16x1 These ...
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Lattice Semiconductor Figure 2-5. Primary Clock Sources PLL Input Clock Input PLL Input Note: Smaller devices have two PLLs. Secondary Clock Sources LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at every PFU. ...
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Lattice Semiconductor Figure 2-6. Secondary Clock Sources From Routing From Routing Clock Input From Routing From Routing Clock Routing The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net- work per quadrant. ...
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Lattice Semiconductor Figure 2-8. Per Quadrant Secondary Clock Selection 20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals Figure 2-9. Slice Clock Selection Primary Clock Secondary Clock sysCLOCK Phase Locked Loops (PLLs) The PLL clock input, ...
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Lattice Semiconductor Figure 2-10. PLL Diagram RST Input Clock Divider (CLKI) CLKI (from routing or external pin) Feedback CLKFB from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) Figure 2-11 shows the available ...
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Lattice Semiconductor For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two ...
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Lattice Semiconductor Table 2-6. sysMEM Block Configurations Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to ...
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Lattice Semiconductor Figure 2-14. sysMEM Memory Primitives AD[12:0] DI[35:0] CLK CE RST WE CS[2:0] Single Port RAM AD[12:0] CLK CE RST CS[2:0] The EBR memory supports three forms of write behavior for single port or dual port operation: 1. Normal ...
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Lattice Semiconductor Figure 2-15. Memory Core Reset RSTA RSTB GSRN For further information on sysMEM EBR block, see the details of additional technical documentation at the end of this data sheet. EBR Asynchronous Reset EBR asynchronous reset or GSR (if ...
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Lattice Semiconductor Figure 2-17. PIC Diagram TD OPOS1 ONEG1 OPOS0 ONEG0 INCK INDD INFF IPOS0 IPOS1 CLK CE LSR GSRN DQS DDRCLKPOL In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential ...
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Lattice Semiconductor Figure 2-18. Group of Seven PIOs Four PICs Figure 2-19. DQS Routing DQS PIO The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic block. These blocks contain registers ...
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Lattice Semiconductor in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require- ...
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Lattice Semiconductor Figure 2-21. Input Register DDR Waveforms DI (In DDR Mode) DQS DQS Delayed D0 D2 Figure 2-22. INDDRXB Primitive Output Register Block The output register block provides the ability to register signals from the core of the device ...
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Lattice Semiconductor Figure 2-23. Output Register Block ONEG0 From Routing OPOS0 CLK1 Figure 2-24. ODDRXB Primitive Tristate Register Block The tristate register block provides the ability to register tri-state control signals from the core of the device before they are ...
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Lattice Semiconductor Figure 2-25. Tristate Register Block TD ONEG1 From Routing OPOS1 CLK1 Control Logic Block The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is selected from one ...
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Lattice Semiconductor Figure 2-26. DQS Local Bus Delay Control Bus Polarity Control Bus DQS Bus DQS DQS Figure 2-27. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. ...
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Lattice Semiconductor Polarity Control Logic In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the internal system Clock (during the READ cycle) is unknown. The LatticeXP family contains dedicated circuits to transfer ...
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Lattice Semiconductor Figure 2-28. LatticeXP Banks V CCIO7 V REF1(7) V REF2(7) GND V CCIO6 V REF1(6) V REF2(6) GND Note: N and M are the maximum number of I/Os per bank. LatticeXP devices contain two types of sysIO buffer ...
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Lattice Semiconductor Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when V After the POR signal is deactivated, the FPGA core logic becomes active the user’s responsibility to ensure that all other V banks ...
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Lattice Semiconductor Table 2-8. Supported Output Standards Output Standard Single-ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 HSTL18 Class I, II, III HSTL15 Class ...
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Lattice Semiconductor Table 2-9. Characteristics of Normal, Off and Sleep Modes Characteristic SLEEPN Pin Static Icc I/O Leakage Power Supplies VCC/VCCIO/VCCAUX Logic Operation I/O Operation JTAG and Programming circuitry EBR Contents and Registers SLEEPN Pin Characteristics The SLEEPN pin behaves ...
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Lattice Semiconductor Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lat- ticeXP devices. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial ...
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Lattice Semiconductor master serial clock is 2.5MHz. Table 2-10 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is selected during the design process, the following sequence takes place: 1. User selects a different Master ...
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... CCAUX © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Hot Socketing Specifications Symbol Parameter I Input or I/O Leakage Current DK 1. Insensitive to sequence CC, CCAUX 2. 0 ≤ V ≤ V (MAX ≤ V ≤ CCAUX 3. ...
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... LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C All LFXP ‘C’ Devices LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3C LFXP6C 5 LFXP10C LFXP15C LFXP20C All LFXP ‘C’ Devices 3-3 DC and Switching Characteristics LatticeXP Family Data Sheet Min. Typ. Max. — — 10 — — 40 -30 — ...
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... A 6. Per bank Over Recommended Operating Conditions Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C All LFXP3E/C LFXP6E/C LFXP10E/C LFXP15E/C LFXP20E/C 6 All All 3-4 DC and Switching Characteristics LatticeXP Family Data Sheet 5 Typ. ...
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... Assume normal bypass capacitor/decoupling capacitor across the supply =25°C, power supplies at nominal voltage Over Recommended Operating Conditions Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C LFXP10E /C LFXP15E /C LFXP20E /C All 3-5 DC and Switching Characteristics LatticeXP Family Data Sheet 7 Typ. Units ...
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... A 7. When programming via JTAG. DC and Switching Characteristics Device LFXP3E LFXP6E LFXP10E LFXP15E LFXP20E LFXP3C LFXP6C LFXP10C LFXP15C LFXP20C LFXP3E /C LFXP6E /C LFXP10E /C LFXP15E /C LFXP20E /C 7 All 3-6 LatticeXP Family Data Sheet .6 Typ Units 30 mA ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.135 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 LVCMOS 1.2 1.14 LVTTL 3.135 PCI33 3.135 SSTL18 Class I 1.71 SSTL2 Class I, II 2.375 SSTL3 Class I, II ...
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Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 0.8 LVTTL -0.3 0.8 LVCMOS 2.5 -0.3 0.7 LVCMOS 1.8 -0.3 0.35V CCIO LVCMOS 1.5 -0.3 0.35V CCIO LVCMOS 1.2 -0.3 0.42 ...
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Lattice Semiconductor sysIO Differential Electrical Characteristics LVDS Parameter Symbol Parameter Description V V Input Voltage INP, INM V Differential Input Threshold THD V Input Common Mode Voltage CM I Input current IN V Output high voltage for ...
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Lattice Semiconductor Differential HSTL and SSTL Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow- able single-ended output classes (class I and class II) are supported in this mode. LVDS25E The top and ...
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Lattice Semiconductor Figure 3-2. BLVDS Multi-point Output Example Heavily loaded backplane, effective ohms differential 2. Table 3-2. BLVDS DC Conditions Symbol Z OUT R TLEFT R TRIGHT ...
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Lattice Semiconductor LVPECL The LatticeXP devices support differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. ...
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Lattice Semiconductor Figure 3-4. RSDS (Reduced Swing Differential Standard) VCCIO = 2.5V VCCIO = 2.5V On-chip Emulated RSDS Buffer Table 3-4. RSDS DC Conditions Parameter Z OUT ...
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Lattice Semiconductor Typical Building Block Function Performance Pin-to-Pin Performance (LVCMOS25 12 mA Drive) Function Basic Functions 16-bit decoder 32-bit decoder 64-bit decoder 4:1 MUX 8:1 MUX 16:1 MUX 32:1 MUX Register to Register Performance Function Basic Functions 16-bit decoder 32-bit ...
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Lattice Semiconductor Derating Logic Timing Logic timing provided in the following sections of this data sheet and in the ispLEVER design tools are worst case numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process ...
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Lattice Semiconductor LatticeXP External Switching Characteristics Parameter Description General I/O Pin Parameters (Using Primary Clock without PLL) t Clock to Output - PIO Output Register CO t Clock to Data Setup - PIO Input Register SU t Clock to Data ...
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Lattice Semiconductor Figure 3-5. DDR Timings DQ and DQS Read Timings DQS DQ DQ and DQS Write Timings DQS DQ DC and Switching Characteristics LatticeXP Family Data Sheet t DVADQ t DVEDQ t DQVBS t DQVAS 3-17 ...
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Lattice Semiconductor LatticeXP Internal Timing Parameters Parameter PFU/PFF Logic Mode Timing t LUT4 Delay ( Inputs to F Output) LUT4_PFU t LUT6 Delay ( Inputs to OFX Output) LUT6_PFU t Set/Reset to Output of PFU LSR_PFU ...
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Lattice Semiconductor LatticeXP Internal Timing Parameters Parameter Reset To Output Delay Time from EBR Output t RSTO_EBR Register PLL Parameters t Reset Recovery to Rising Clock RSTREC t Reset Signal Setup Time RSTSU 1. Internal parameters are characterized but not ...
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Lattice Semiconductor Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] DO[1:0] CK WRE AD AD[3:0] D DI[1:0] DO[1:0] Old Data Old ...
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Lattice Semiconductor EBR Memory Timing Diagrams Figure 3-8. Read Mode (Normal) CLKA CSA WEA ADA DIA D0 DOA Note: Input data and address are registered at the positive edge of the clock and output data appears ...
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Lattice Semiconductor Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only) CLKA CSA WEA ADA DIA DOA Note: Input data and address are registered at the positive edge of the ...
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Lattice Semiconductor LatticeXP Family Timing Adders Buffer Type Description Input Adjusters LVDS25E LVDS 2.5 Emulated LVDS25 LVDS BLVDS25 BLVDS LVPECL33 LVPECL HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II HSTL18_III HSTL_18 class III HSTL18D_I Differential HSTL 18 class I HSTL18D_II ...
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Lattice Semiconductor LatticeXP Family Timing Adders Buffer Type Description HSTL15_I HSTL_15 class I HSTL15_III HSTL_15 class III HSTL15D_I Differential HSTL 15 class I HSTL15D_III Differential HSTL 15 class III SSTL33_I SSTL_3 class I SSTL33_II SSTL_3 class II SSTL33D_I Differential SSTL_3 ...
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Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB Output Clock Frequency (CLKOP, CLKOS) OUT f K-Divider Output Frequency (CLKOK) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics ...
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Lattice Semiconductor LatticeXP sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t Clock to Dout in Flowthrough Mode CODO t CS[0:1] Setup Time ...
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Lattice Semiconductor Flash Download Time Symbol PROGRAMN Low-to- t High. Transition to Done REFRESH High. JTAG Port Timing Specifications Symbol f MAX t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] ...
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Lattice Semiconductor Switching Test Conditions Figure 3-13 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Figure 3-5. Figure 3-13. Output Test Load, LVTTL ...
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... PCLK[T, C]_[n:0]_[3:0] [LOC]DQS[num] © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Signal Descriptions (Cont.) Signal Name Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.) TMS TCK TDI TDO V CCJ Configuration Pads (used during sysCONFIG) CFG[1:0] INITN PROGRAMN DONE CCLK BUSY CSN CS1N WRITEN ...
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Lattice Semiconductor PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin PICs Associated with DQS Strobe P[Edge] [n-4] P[Edge] [n-3] P[Edge] [n-2] P[Edge] [n-1] P[Edge] [n] P[Edge] [n+1] P[Edge] [n+2] P[Edge] [n+3] Notes: 1. “n” is ...
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Lattice Semiconductor Pin Information Summary Pin Type Single Ended User I/O 2 Differential Pair User I/O Dedicated Configuration Muxed TAP Dedicated (total without supplies CCAUX V CCPLL Bank0 Bank1 Bank2 Bank3 V CCIO Bank4 Bank5 Bank6 Bank7 ...
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Lattice Semiconductor Pin Information Summary Pin Type 256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA Single Ended User I/O 188 2 Differential Pair User I/O 76 Dedicated 11 Configuration Muxed 14 TAP ...
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Lattice Semiconductor Power Supply and NC Connections Signals 100 TQFP 144 TQFP V 28, 77 14, 39, 73, 112 133 CCIO0 V 82 119 CCIO1 CCIO2 CCIO3 V 47 61, 68 ...
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Lattice Semiconductor LFXP3 Logic Signal Connections: 100 TQFP Pin Number Pin Function 1 CFG1 2 DONE 3 PROGRAMN 4 CCLK 5 PL3A 6 PL3B 7 VCCIO7 8 PL5A 9 PL6B 10 GNDIO7 11 PL7A 12 PL7B 13 PL8A 14 PL8B ...
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Lattice Semiconductor LFXP3 Logic Signal Connections: 100 TQFP (Cont.) Pin Number Pin Function 44 GNDIO4 45 PB15A 46 PB15B 47 VCCIO4 48 PB19A 49 PB19B 50 PB24A 51 PR18B 52 GNDIO3 53 PR18A 54 PR15B 55 PR14A 56 PR13B 57 ...
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Lattice Semiconductor LFXP3 Logic Signal Connections: 100 TQFP (Cont.) Pin Number Pin Function 88 PT14B 89 PT13B 90 GNDIO0 91 PT13A 92 PT12B 93 PT12A 94 VCCIO0 95 PT9A 96 PT8A 97 PT6A 98 PT5A 99 GND 100 CFG0 1. ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP LFXP3 Pin Number Pin Function Bank Differential 1 PROGRAMN 7 2 CCLK GND 4 PL2A 7 5 PL2B 7 6 PL3A 7 7 PL3B 7 8 VCCIO7 ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 47 PB11A 5 48 PB11B 5 49 VCCIO5 5 50 PB12A 5 51 PB12B 5 52 PB13A 5 53 PB13B 5 - ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 93 PR9A 2 94 PR8B 2 95 PR8A 2 96 PR7B 2 97 PR7A 2 98 VCCIO2 2 99 PR6B 2 100 ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 139 PT6A 0 140 PT5A 0 141 PT3B 0 142 CFG0 0 143 CFG1 0 144 DONE 0 1. Applies to LFXP ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP LFXP3 Pin Number Pin Function Bank Differential 1 CFG1 0 2 DONE 0 3 PROGRAMN 7 4 CCLK GND 6 PL2A 7 7 GNDIO7 7 8 PL2B ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 47 GNDIO6 6 48 PL18B GND - 50 VCCAUX SLEEPN /TOE - 52 INITN 5 - ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 93 PB19B 4 94 PB20A 4 95 PB20B 4 96 PB21A 4 97 VCCIO4 4 98 PB21B 4 99 PB22A 4 100 ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 139 PR7A 2 140 VCCIO2 2 141 PR6B 2 142 PR5A 2 143 GNDIO2 2 144 PR4B 2 145 PR4A 2 146 ...
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Lattice Semiconductor LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.) LFXP3 Pin Number Pin Function Bank Differential 185 PT13A 0 186 PT12B 0 187 PT12A 0 188 PT11B 0 189 VCCIO0 0 190 PT11A 0 191 PT10B 0 192 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA LFXP6 Ball Ball Number Function Bank Differential C2 PROGRAMN 7 C1 CCLK 7 - GNDIO7 7 D2 PL3A 7 D3 PL3B 7 D1 PL2A 7 E2 PL5A 7 - GNDIO7 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential K4 PL20A 6 K5 PL20B 6 - GNDIO6 6 N1 PL23B 6 N2 PL21B 6 P1 PL24A 6 P2 PL24B 6 L5 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential R8 PB16A 5 T9 PB16B 5 R9 PB17A 4 - GNDIO4 4 P9 PB17B 4 T10 PB18A 4 T11 PB18B 4 R10 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential L15 PR21B 3 L14 PR21A 3 - GNDIO3 3 L12 PR17B 3 M16 PR20B 3 N16 PR20A 3 K14 PR19B 3 K15 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential E16 TDO - D16 VCCJ - D14 TDI - C14 TMS - B14 TCK - - GNDIO1 1 A15 PT31B 1 B15 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential E8 PT13B 0 D8 PT12A 0 A6 PT11B 0 - GNDIO0 0 C6 PT11A 0 E7 PT10B 0 D7 PT10A 0 A5 ...
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Lattice Semiconductor LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.) LFXP6 Ball Ball Number Function Bank Differential K10 GND - K7 GND - K8 GND - K9 GND - L11 GND - L6 GND - T1 GND - T16 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA LFXP15 Ball Ball Number Function Bank Differential C2 PROGRAMN 7 C1 CCLK 7 - GNDIO7 7 - GNDIO7 7 D2 PL7A 7 D3 PL7B 7 D1 PL9A 7 E2 PL10B ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential L4 PL32A 6 - GNDIO6 6 K4 PL33A 6 K5 PL33B 6 N1 PL35A 6 N2 PL36B 6 P1 PL37A 6 P2 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential T7 PB23B 5 - GNDIO5 5 P8 PB24A 5 T8 PB24B 5 R8 PB25A 5 T9 PB25B 5 R9 PB26A 4 P9 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential P16 PR37B 3 R16 PR37A 3 M15 PR36B 3 N14 PR35A 3 - GNDIO3 3 M14 PR33B 3 L13 PR33A 3 L15 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential - GNDIO2 2 F15 PR10B 2 E15 PR9A 2 F14 PR8B 2 E14 PR8A 2 D15 PR7B 2 C15 PR7A 2 - ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential A9 PT27A 1 C9 PT26B 1 C8 PT26A 1 E9 PT25B 0 - GNDIO0 0 B8 PT25A 0 A8 PT24B 0 A7 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential G10 GND - G7 GND - G8 GND - G9 GND - H10 GND - H7 GND - H8 GND - H9 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential L7 VCCIO5 5 L8 VCCIO5 5 J6 VCCIO6 6 K6 VCCIO6 6 G6 VCCIO7 7 H6 VCCIO7 7 1. Applies to LFXP ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA LFXP10 Ball Ball Number Function Bank Diff. Dual Function F4 PROGRAMN CCLK GNDIO7 PL2A PL2B ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function U1 PL25A 6 T LLM0_PLLT_IN_A T2 PL25B 6 C LLM0_PLLC_IN_A 3 V1 PL26A PL26B 6 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function Y10 PB11B 5 C AA7 PB12A 5 T AB7 PB12B 5 C VREF2_5 Y7 PB13A GNDIO5 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function AA20 PB36B 4 C AB21 PB37A 4 T AA21 PB37B 4 C AA22 PB38A 4 T Y21 PB38B 4 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function M21 VCCP1 - - - GNDIO2 M22 PR18B L22 PR18A 2 T K22 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function C20 PT38A 1 T C21 PT37B 1 C C22 PT37A 1 T B22 PT36B 1 C A21 PT36A 1 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function A7 PT13A PT12B PT12A 0 T C10 PT11B PT11A 0 ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function K11 GND - - K12 GND - - K13 GND - - K14 GND - - K9 GND - ...
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Lattice Semiconductor LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.) LFXP10 Ball Ball Number Function Bank Diff. Dual Function G7 VCCAUX - - T16 VCCAUX - - T7 VCCAUX - - G10 VCCIO0 0 - G11 VCCIO0 0 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA LFXP15 Ball Ball Number Function Bank Differential F5 PROGRAMN 7 E3 CCLK 7 C1 PL2B 7 - GNDIO7 7 G5 PL3A 7 G6 PL3B 7 F4 PL4A 7 F3 PL4B ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential VCCP0 - N2 GNDP0 - ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential T6 PL41A 6 T5 PL41B 6 - GNDIO6 6 U3 PL42A 6 U4 PL42B 6 V4 PL43A 6 1 SLEEPN / W4 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential AB5 PB16A 5 AB6 PB16B 5 AA8 PB17A 5 AA9 PB17B 5 W10 PB18A 5 - GNDIO5 5 V10 PB18B 5 AB7 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential AB19 PB37A 4 AB20 PB38B 4 - GNDIO4 4 V15 PB39A 4 U15 PB39B 4 Y15 PB40A 4 W15 PB40B 4 AA16 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential R18 PR38B 3 R17 PR38A 3 Y22 PR37B 3 Y21 PR37A 3 W22 PR36B 3 W21 PR35A 3 P17 PR34B 3 P18 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential J21 PR20B 2 J22 PR20A 2 K18 PR19B 2 K19 PR18A 2 - GNDIO2 2 K21 PR17B 2 K20 PR17A 2 H21 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential D18 - - E18 - - C19 - - C18 - - C21 - - - GNDIO1 1 B21 - - E17 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential A14 PT30B 1 B14 PT29A 1 C12 PT28B 1 B12 PT28A 1 - GNDIO1 1 D12 PT27B 1 E12 PT27A 1 A13 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential B3 PT8B 0 A3 PT8A 0 - GNDIO0 0 D7 PT7B 0 C7 PT7A 0 B2 PT6B 0 C2 PT5A 0 C3 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential J15 GND - J8 GND - J9 GND - K10 GND - K11 GND - K12 GND - K13 GND - K14 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential G9 VCC - H15 VCC - H8 VCC - J16 VCC - J7 VCC - K16 VCC - K17 VCC - K6 ...
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Lattice Semiconductor LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.) LFXP15 Ball Ball Number Function Bank Differential H13 VCCIO1 1 K15 VCCIO2 2 L15 VCCIO2 2 L16 VCCIO2 2 L17 VCCIO2 2 M15 VCCIO3 3 M16 VCCIO3 3 M17 ...
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Lattice Semiconductor Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a ...
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... The markings appear as follows: © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Conventional Packaging Part Number I/Os LFXP3C-3Q208C 136 LFXP3C-4Q208C 136 LFXP3C-5Q208C 136 LFXP3C-3T144C 100 LFXP3C-4T144C 100 LFXP3C-5T144C 100 LFXP3C-3T100C 62 LFXP3C-4T100C 62 LFXP3C-5T100C 62 Part Number I/Os LFXP6C-3F256C 188 LFXP6C-4F256C 188 LFXP6C-5F256C 188 LFXP6C-3Q208C 142 LFXP6C-4Q208C 142 LFXP6C-5Q208C 142 ...
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... LFXP15C-5F388C 268 LFXP15C-3F256C 188 LFXP15C-4F256C 188 LFXP15C-5F256C 188 Part Number I/Os LFXP20C-3F484C 340 LFXP20C-4F484C 340 LFXP20C-5F484C 340 LFXP20C-3F388C 268 LFXP20C-4F388C 268 LFXP20C-5F388C 268 LFXP20C-3F256C 188 LFXP20C-4F256C 188 LFXP20C-5F256C 188 Part Number I/Os LFXP3E-3Q208C 136 LFXP3E-4Q208C 136 LFXP3E-5Q208C 136 LFXP3E-3T144C 100 LFXP3E-4T144C 100 LFXP3E-5T144C ...
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Lattice Semiconductor Part Number I/Os LFXP6E-3F256C 188 LFXP6E-4F256C 188 LFXP6E-5F256C 188 LFXP6E-3Q208C 142 LFXP6E-4Q208C 142 LFXP6E-5Q208C 142 LFXP6E-3T144C 100 LFXP6E-4T144C 100 LFXP6E-5T144C 100 Part Number I/Os LFXP10E-3F388C 244 LFXP10E-4F388C 244 LFXP10E-5F388C 244 LFXP10E-3F256C 188 LFXP10E-4F256C 188 LFXP10E-5F256C 188 Part Number ...
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Lattice Semiconductor Part Number I/Os LFXP20E-3F484C 340 LFXP20E-4F484C 340 LFXP20E-5F484C 340 LFXP20E-3F388C 268 LFXP20E-4F388C 268 LFXP20E-5F388C 268 LFXP20E-3F256C 188 LFXP20E-4F256C 188 LFXP20E-5F256C 188 Part Number I/Os LFXP3C-3Q208I 136 LFXP3C-4Q208I 136 LFXP3C-3T144I 100 LFXP3C-4T144I 100 LFXP3C-3T100I 62 LFXP3C-4T100I 62 Part Number ...
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... LFXP15C-4F484I 300 LFXP15C-3F388I 268 LFXP15C-4F388I 268 LFXP15C-3F256I 188 LFXP15C-4F256I 188 Part Number I/Os LFXP20C-3F484I 340 LFXP20C-4F484I 340 LFXP20C-3F388I 268 LFXP20C-4F388I 268 LFXP20C-3F256I 188 LFXP20C-4F256I 188 Part Number I/Os LFXP3E-3Q208I 136 LFXP3E-4Q208I 136 LFXP3E-3T144I 100 LFXP3E-4T144I 100 LFXP3E-3T100I 62 LFXP3E-4T100I 62 Part Number I/Os LFXP6E-3F256I 188 ...
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Lattice Semiconductor Part Number I/Os LFXP15E-3F484I 300 LFXP15E-4F484I 300 LFXP15E-3F388I 268 LFXP15E-4F388I 268 LFXP15E-3F256I 188 LFXP15E-4F256I 188 Part Number I/Os LFXP20E-3F484I 340 LFXP20E-4F484I 340 LFXP20E-3F388I 268 LFXP20E-4F388I 268 LFXP20E-3F256I 188 LFXP20E-4F256I 188 Industrial (Cont.) Voltage Grade Package 1.2V -3 fpBGA ...
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Lattice Semiconductor Lead-free Packaging Part Number I/Os LFXP3C-3QN208C 136 LFXP3C-4QN208C 136 LFXP3C-5QN208C 136 LFXP3C-3TN144C 100 LFXP3C-4TN144C 100 LFXP3C-5TN144C 100 LFXP3C-3TN100C 62 LFXP3C-4TN100C 62 LFXP3C-5TN100C 62 Part Number I/Os LFXP6C-3FN256C 188 LFXP6C-4FN256C 188 LFXP6C-5FN256C 188 LFXP6C-3QN208C 142 LFXP6C-4QN208C 142 LFXP6C-5QN208C 142 ...
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... Lattice Semiconductor Part Number I/Os LFXP20C-3FN484C 340 LFXP20C-4FN484C 340 LFXP20C-5FN484C 340 LFXP20C-3FN388C 268 LFXP20C-4FN388C 268 LFXP20C-5FN388C 268 LFXP20C-3FN256C 188 LFXP20C-4FN256C 188 LFXP20C-5FN256C 188 Part Number I/Os LFXP3E-3QN208C 136 LFXP3E-4QN208C 136 LFXP3E-5QN208C 136 LFXP3E-3TN144C 100 LFXP3E-4TN144C 100 LFXP3E-5TN144C 100 LFXP3E-3TN100C 62 LFXP3E-4TN100C 62 LFXP3E-5TN100C 62 Part Number ...
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Lattice Semiconductor Part Number I/Os LFXP15E-3FN484C 300 LFXP15E-4FN484C 300 LFXP15E-5FN484C 300 LFXP15E-3FN388C 268 LFXP15E-4FN388C 268 LFXP15E-5FN388C 268 LFXP15E-3FN256C 188 LFXP15E-4FN256C 188 LFXP15E-5FN256C 188 Part Number I/Os LFXP20E-3FN484C 340 LFXP20E-4FN484C 340 LFXP20E-5FN484C 340 LFXP20E-3FN388C 268 LFXP20E-4FN388C 268 LFXP20E-5FN388C 268 LFXP20E-3FN256C 188 ...
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... LFXP15C-4FN484I 300 LFXP15C-3FN388I 268 LFXP15C-4FN388I 268 LFXP15C-3FN256I 188 LFXP15C-4FN256I 188 Part Number I/Os LFXP20C-3FN484I 340 LFXP20C-4FN484I 340 LFXP20C-3FN388I 268 LFXP20C-4FN388I 268 LFXP20C-3FN256I 188 LFXP20C-4FN256I 188 Part Number I/Os LFXP3E-3QN208I 136 LFXP3E-4QN208I 136 LFXP3E-3TN144I 100 LFXP3E-4TN144I 100 LFXP3E-3TN100I 62 LFXP3E-4TN100I 62 Part Number I/Os LFXP6E-3FN256I 188 ...
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Lattice Semiconductor Part Number I/Os LFXP10E-3FN388I 244 LFXP10E-4FN388I 244 LFXP10E-3FN256I 188 LFXP10E-4FN256I 188 Part Number I/Os LFXP15E-3FN484I 300 LFXP15E-4FN484I 300 LFXP15E-3FN388I 268 LFXP15E-4FN388I 268 LFXP15E-3FN256I 188 LFXP15E-4FN256I 188 Part Number I/Os LFXP20E-3FN484I 340 LFXP20E-4FN484I 340 LFXP20E-3FN388I 268 LFXP20E-4FN388I 268 LFXP20E-3FN256I ...
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... PCI: www.pcisig.com © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... DC and Switching Characteristics © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Date Version September 2005 03.0 DC and Switching (cont.) (cont.) Characteristics (cont.) Pinout Information Supplemental Information September 2005 03.1 Pinout Information December 2005 04.0 Introduction Architecture DC and Switching Characteristics Pinout Information Ordering Information February 2006 04.1 Pinout ...