rt9645 Richtek Technology Corporation, rt9645 Datasheet
rt9645
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rt9645 Summary of contents
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... Channels ACPI Regulator General Description The RT9645 is a combo regulator which is compliant to ACPI specification for desktop/server power management and system application. The part features one switching regulator for DDR memory VDDQ power; a second PWM controller for GMCH core power, a LDO controller for FSB_ VTT termination, a LDO controller for 5VSB to 3VSB conversion ...
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... R Q4 OCSET2 15 ISNS2 PHASE 5 COMP2 LGATE 6 FB2 Q5 18 VTT_DRV 17 VTT_SEN COMP1 Q6 1 SB3V_DRV 24 SB3V_SEN VCC_DRV 4 SS2/EN2 SB5V_DRV 16 VTT_EN 23 S3 Figure 2. RT9645 Typical Application for AMD K8 7 5VDL BOOT R OCSET1 10 ISNS 8 UGATE Q1 9 PHASE 12 LGATE Q2 19 GND 13 COMP1 14 FB1 ...
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... SS2/EN2 PWM2_EN (Internal) PWM2 UV Protection_EN DS9645-00 August 2007 Preliminary ~3Tss VCC12 - V POR D 5VSB ~Tss ~Tss Figure 3. RT9645 Timing Diagram for Intel CPU ~3Tss VCC12 - V POR D 5VSB ~Tss ~Tss ~Tss Figure 4. RT9645 Timing Diagram for AMD CPU V EN2 PWM2 (Output) Figure 5 ...
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... RT9645 Functional Pin Description Pin No. Pin Name 1 SB3V_DRV Gate Drive for 3.3VSB Linear Controller. The pin will be high in S0, S3 and S5 state. 2 VDD 3 PWM2 4 SS2/EN2 5 COMP2 6 FB2 7 BOOT 8 UGATE 9 PHASE 10 ISNS 11 PVIN 12 LGATE 13 COMP1 14 FB1 15 ISNS2 16 VTT_EN 17 VTT_SEN 18 VTT_DRV 19 GND 20 SB5V_DRV 21 VCC_DRV ...
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... SB3V Fault (UV &OC) Thermal shut_down GND DS9645-00 August 2007 Preliminary FB2 REF Digital & Peripheral Control or Back S5 Hiccup COMP1 EN_Detect - - + + + - V REF Oscillator - + 40uA - + PVIN VDD RT9645 BOOT UGATE PHASE PVIN LGATE I OC2 40uA ISNS2 I OC1 ISNS VCC_DRV SB5V_DRV www.richtek.com 5 ...
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... RT9645 Absolute Maximum Ratings Supply Voltage, V ------------------------------------------------------------------------------------- 7V DD Supply Voltage, PVIN ----------------------------------------------------------------------------------- 16V PHASE to GND DC ------------------------------------------------------------------------------------------------------------ −0. < 200ns ----------------------------------------------------------------------------------------------------- − BOOT to GND DC ------------------------------------------------------------------------------------------------------------ −0.3V to 20V < 200ns ----------------------------------------------------------------------------------------------------- −0.3V to 22V − V BOOT, V ---------------------------------------------------------------------------------- 16V BOOT PHASE UGATE Voltage ------------------------------------------------------------------------------------------- V LGATE Voltage -------------------------------------------------------------------------------------------- GND − 0.3V to VDD + 0.3V Input, Output or I/O Voltage ---------------------------------------------------------------------------- GND − 0. Power Dissipation 25° ...
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... UV2 SS2 SS2/EN2 V EN2 PT_EN2 12V OH3 PVIN SC3 VTT_DRV 0.6V SK3 VTT DRV V UV3 V 3VSB I SC4 I OC4 V UV4 SHDN RT9645 Min Typ 265 300 -- 1 0.784 0 0.1 0 0.5 -- 3.6 10 ...
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... RT9645 Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability ...
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... Refer to Figure 3 and Figure 4 for the detailed timing diagrams. DS9645-00 August 2007 Preliminary Transition When S3 goes LOW but S5 still HIGH ,the RT9645 will disable FSB_VTT regulators. SB5V_DRV and VCC_DRV will go low to continually power on 5VDL rail. The memory power Transition ...
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... I > L(MAX) OUT(MAX) L ΔI = inductor ripple current L If Low side MOSFET with R DS(ON) OCP threshold current is about 20A. Once OCP is triggered, the RT9645 enters S5 sleep state. UGATE (20V/Div) LGATE (10V/Div) V OUT (1V/Div) I LOAD (10A/Div) Time (250μs/Div) Figure 6. Over Cuuent Protection ...
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... OUT I ESR × × OSC = × × − OUT , gate driving requirements, and DS(ON COND _ UPPER SW _ UPPER 1 × × + × × DS(ON) OUT IN 2 RT9645 − ( OUT + × RISE FALL OSC www.richtek.com 11 ...
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... RT9645 where T and T are rising and falling time of V RISE FALL upper MOSFET respectively. R DS(ON) simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is expressed as : ...
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... Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com DETAIL A Pin #1 ID and Tie Bar Mark Options Dimensions In Inches Min Max 0.031 0.039 0.000 0.002 0.007 0.010 0.007 0.012 0.156 0.159 0.091 0.108 0.156 0.159 0.091 0.108 0.020 0.014 0.018 RT9645 1 2 www.richtek.com 13 ...