gal26clv12 Lattice Semiconductor Corp., gal26clv12 Datasheet
gal26clv12
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gal26clv12 Summary of contents
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... ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL26CLV12D maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's 2 advanced 3.3V E CMOS process, which combines CMOS with ...
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... GAL26CLV12D Ordering Information Commercial Grade Specifications Part Number Description GAL26CLV12D Device Name Speed (ns Low Power Power Specifications GAL26CLV12 ...
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... GAL26CLV12D OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations Each of the Macrocells of the GAL26CLV12D has two primary func- tional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (S0 and S1), which are nor- mally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page ...
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... Registered Mode ACTIVE LOW Combinatorial Mode ACTIVE LOW Specifications GAL26CLV12 ACTIVE HIGH ACTIVE HIGH ...
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... GAL26CLV12D Logic Diagram/JEDEC Fuse Map 0000 0052 . . . 0468 2 0520 . . . 0936 3 0988 . . . 1404 4 1456 . . . 1872 5 1924 . . . . 2444 6 2496 . . . . . 3120 8 3172 . . . . . 3796 9 3848 . . . . 4368 10 4420 . . . 4836 11 4888 . . . 5304 12 5356 . . . 5772 13 5824 . . . 6240 14 6292 6368, 6369 ... Byte 7 Byte 6 Byte 5 Byte Specifications GAL26CLV12 ...
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... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and T Specifications GAL26CLV12 Recommended Operating Conditions (1) Commercial Devices: ...
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... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL26CLV12 Over Recommended Operating Conditions TYPICAL UNITS COM COM -5 -7 MIN. MAX. MIN. MAX. ...
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... OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING CLK REGISTERED OUTPUT Synchronous Preset Specifications GAL26CLV12 INPUT or VALID INPUT I/O FEEDBACK t pd CLK REGISTERED OUTPUT t en CLK REGISTERED FEEDBACK INPUT or I/O FEEDB ACK DRIVI NG AR ...
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... Output Load Conditions (see figure) Test Condition A B High Z to Active High at 1.9V High Z to Active Low at 1.0V C Active High to High Z at 1.9V Active Low to High Z at 1.0V Specifications GAL26CLV12 su+ co) f Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The ...
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... These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins on the GAL26CLV12D also have built-in ac- tive pull-ups result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground ...
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... Device Pin Reset to Logic "0" chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL26CLV12D. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. ...
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... GAL26CLV12D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 RISE 1.05 FALL 1 0.95 0.9 3 3.15 3.3 3.45 3.6 Supply Voltage (V) Normalized Tpd vs Temp 1.3 RISE 1.2 FALL 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.1 -0.2 -0.3 -0 Number of Outputs Switching Delta Tpd vs Output Loading RISE ...
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... GAL26CLV12D: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.8 0.6 0.4 0 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 3 3.15 3.3 3.45 Supply Voltage (V) Delta Icc vs Vin (1 input 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Vin (V) Specifications GAL26CLV12 Voh vs Ioh 3 2 Ioh(mA) Normalized Icc vs Temp 1 ...