m52s16161a Elite Semiconductor Memory Technology Inc., m52s16161a Datasheet - Page 14

• Manufacturer Part Number: m52s16161a
• Description: 512k X 16bit X 2banks Mobile Synchronous Dram
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
QC
*Note: 1. Minimum row cycle times is required to complete internal DRAM operation.
Elite Semiconductor Memory Technology Inc.
A10 /AP
CLOCK
ADDR
CL =3
CL =2
DQM
CKE
CAS
RAS
WE
BA
CS
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
3. Access time from Row active command. tcc*(t
4. Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
precharge. Last valid output will be Hi-Z(t
Burst can’t end in Full Page Mode.
0
Row Active
(A-Ba nk)
Ra
Ra
1
t
2
R C D
*Note3
t
R AC
3
*No te3
t
R AC
(A-B ank)
Ca0
Read
4
5
Qa0
t
S AC
6
t
RC
Qa0
Qa1
t
t
O H
S AC
SHZ
*Note1
*Note 2
7
Precharge
(A-Bank)
) after the clock.
Qa1
Qa2
RCD
t
O H
8
+CAS latency-1)+t
Qa2
Qa3
9
HIGH
Qa3
t
SH Z
10
Row Active
(A-Ba nk )
*Note4
Rb
Rb
t
S HZ
11
*Note4
SAC
12
13
(A-Ban k)
W ri te
Db0
Db0
Cb0
14
Revision : 1.6
Publication Date : May 2009
Db1
Db1
M52S16161A
15
Db2
Db2
16
Db3
Db3
17
t
RDL
t
RDL
18
Precharge
(A-Ban k)
14/32
: Don't care
19
20