f25l04ua Elite Semiconductor Memory Technology Inc., f25l04ua Datasheet - Page 15

• Manufacturer Part Number: f25l04ua
• Description: Only Mbit Serial Flash Memory
• Manufacturer: Elite Semiconductor Memory Technology Inc.

ESMT
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with
the Enable-Write-Status-Register (EWSR) instruction to write
new values to the BP1, BP0, and BPL bits of the status register.
The
immediately after the execution of the Enable-Write-Status
-Register instruction (very next instruction bus cycle). This
two-step instruction sequence of the EWSR instruction followed
by the WRSR instruction works like SDP (software data
protection) command structure which prevents any accidental
alteration of the status register values. The Write-Status-Register
instruction will be ignored when WP is low and BPL bit is set to
“1”. When the WP is low, the BPL bit can only be set from “0” to
“1” to lockdown the status register, but cannot be reset from “1” to
“0”.
Figure 13 : ENABLE-WRITE-STATUS-REGISTER (EWSR) AMD WRITE-STATUS-REGISTER (WRSR) SEQUENCE
Elite Semiconductor Memory Technology Inc.
Write-Status-Register
SCK
SO
CE
SI
MODE0
MODE3
MSB
0 1 2 3 4 5 6 7
instruction
50
HIGH IMPENANCE
must
be
executed
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, and BP1 bits in the status register
can all be changed. As long as BPL bit is set to 0 or WP pin is
driven high (V
at the end of the WRSR instruction, the BP0, BP1, and BPL bit in
the status register can all be altered by the WRSR instruction. In
this case, a single WRSR instruction can set the BPL bit to “1” to
lock down the status register as well as altering the BP0 and BP1
bit at the same time. See Table 3 for a summary description of
command sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed. See Figure
13 for EWSR and WRSR instruction sequences.
WP and BPL functions. CE must be driven low before the
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MSB
01
IH
) prior to the low-to-high transition of the CE pin
7 6 5 4 3 2 1 0
REGISTER IN
Publication Date: Jan. 2009
Revision:
STATUS
F25L04UA
1.2
15/25