as7c31024a-20tji ETC-unknow, as7c31024a-20tji Datasheet - Page 2

• Manufacturer Part Number: as7c31024a-20tji
• Description: 5v/3.3v 128kx8 Cmos Sram Evolutionary Pinout
• Manufacturer: ETC-unknow

Functional description
The AS7C1024A and AS7C31024A are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as
131,012 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I
static, then full standby power is reached (I
conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written
on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive
I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t Care, L = Low, H = High
2/6/01; V.0.9
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
CE1
H
X
L
L
L
CC
relative to GND
CE2
H
H
H
X
L
Parameter
CC
AA
applied
, t
WE
H
H
X
X
L
RC
SB1
, t
). For example, the AS7C31024A is guaranteed not to exceed 36mW under nominal full standby
WC
) of 10/12/15/20 ns with output enable access times (t
Alliance Semiconductor
OE
H
X
X
X
L
AS7C31024A
AS7C1024A
Both
Both
Both
Both
Both
®
Symbol
T
I
T
High Z
High Z
High Z
V
V
V
OUT
P
D
bias
Data
stg
t1
t1
t2
D
D
OUT
IN
–0.50
–0.50
-0.50
Min
–65
–55
–
–
OE
) of 3/3/4/5 ns are ideal for high
Output disable (I
V
Standby (I
Standby (I
CC
+150
+125
+7.0
+5.0
Max
Write (
1.0
Read (I
20
+0.50
Mode
SB
AS7C31024A
power. If the bus is
AS7C1024A
SB
SB
ICC
CC
, I
, I
)
)
SB1
SB1
P. 2 of 8
CC
Unit
)
)
mA
W
)
V
V
V
C
C