bs62lv2001ti Brillance Semiconductor, bs62lv2001ti Datasheet

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bs62lv2001ti

Manufacturer Part Number
bs62lv2001ti
Description
Very Power/voltage Cmos Sram 256k
Manufacturer
Brillance Semiconductor
Datasheet
1.BS62LV2001TI.pdf (10 pages)
R0201-BS62LV2001
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
• High speed access time :
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
• All I/O pins are 3V/5V tolerant
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
FEATURES
PRODUCT FAMILY
VCC
CE2
A11
A13
A15
A17
A16
A14
A12
Vcc = 3.0V
Vcc = 5.0V
WE
-70
-10
A9
A8
A7
A6
A5
A4
GND
DQ0
DQ1
DQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
BSI
100ns(Max.) at Vcc = 3.0V
70ns(Max.) at Vcc = 3.0V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV2001TC
BS62LV2001STC
BS62LV2001TI
BS62LV2001STI
0.1uA (Typ.) CMOS standby current
0.6uA (Typ.) CMOS standby current
C-grade : 20mA (Max.) operating current
C-grade : 35mA (Max.) operating current
BS62LV2001SC
BS62LV2001SI
I- grade : 25mA (Max.) operating current
I- grade : 40mA (Max.) operating current
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
. reserves the right to modify document contents without notice.
The BS62LV2001 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
1
BLOCK DIAGRAM
DESCRIPTION
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
A15
A16
A14
A12
Vdd
Gnd
A13
A17
WE
OE
OE
A7
A6
A5
A4
Address
Buffer
Input
8
Control
8
20
Output
Buffer
Buffer
Data
Input
Data
Decoder
Row
8
1024
8
BS62LV2001
A11
A9
Address Input Buffer
Column Decoder
Memory Array
A8 A3 A2 A1
Sense Amp
Write Driver
Column I/O
1024 x 2048
2048
256
16
Revision 2.5
April 2002
A0
A10

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bs62lv2001ti Summary of contents

Page 1

... All I/O pins are 3V/5V tolerant PRODUCT FAMILY PIN CONFIGURATIONS 1 32 A11 A13 CE2 BS62LV2001TC 7 26 A15 BS62LV2001STC VCC BS62LV2001TI 24 A17 BS62LV2001STI 10 23 A16 A14 A12 A17 1 32 VCC A16 ...

Page 2

BSI PIN DESCRIPTIONS Name A0-A17 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0 – DQ7 Data Input/Output Ports Vcc Gnd TRUTH TABLE MODE WE X Not selected ...

Page 3

BSI DC ELECTRICAL CHARACTERISTICS PARAMETER PARAMETER NAME Guaranteed Input Low V IL (2) Voltage Guaranteed Input High V IH (2) Voltage I Input Leakage Current IL I Output Leakage Current OL V Output Low Voltage OL V Output High Voltage ...

Page 4

BSI AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level AC TEST LOADS AND WAVEFORMS Ω 1269 3.3V OUTPUT OUTPUT 100PF INCLUDING Ω 1404 JIG AND SCOPE FIGURE 1A THEVENIN EQUIVALENT 667 ...

Page 5

BSI SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 ADDRESS D OUT (1,3,4) READ CYCLE2 CE1 CE2 D OUT (1,4) READ CYCLE3 ADDRESS OE CE1 CE2 D OUT NOTES high for read Cycle. 2. Device is continuously selected ...

Page 6

BSI AC ELECTRICAL CHARACTERISTICS WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME t t AVAX E1LWH AVWL AVWH WLWH WHAX WR1 t t E2LAX WR2 t ...

Page 7

BSI (1,6) WRITE CYCLE2 ADDRESS CE1 CE2 WE D OUT D IN NOTES must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and ...

Page 8

BSI ORDERING INFORMATION BS62LV2001 STSOP - 32 R0201-BS62LV2001 BS62LV2001 SPEED 70: 70ns 10: 100ns GRADE + - + PACKAGE T: TSOP (8mm ...

Page 9

BSI PACKAGE DIMENSIONS (continued) TSOP - 32 SOP -32 R0201-BS62LV2001 b WITH PLATING BASE METAL SECTION A-A 9 BS62LV2001 Revision 2.5 April 2002 ...

Page 10

BSI REVISION HISTORY Revision Description 2.2 2001 Data Sheet release 2.3 Modify Standby Current (Typ. and Max.) 2.4 To add DICE form 2.5 Modify some AC parameters. Modify 5V ICCSB1_Max(I-grade) from 10uA to 25uA. R0201-BS62LV2001 R0201-BS62LV2001 Date Apr. 15, 2001 ...

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