la-ispmach4032v Lattice Semiconductor Corp., la-ispmach4032v Datasheet

la-ispmach4032v

Manufacturer Part Number

la-ispmach4032v

Description

3.3v/1.8v In-system Programmable Superfast High Density Plds Tm

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.LA-ISPMACH4032V.pdf (42 pages)

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July 2008

Features

■ High Performance

■ Ease of Design

■ Zero Power (LA-ispMACH 4000Z)

■ AEC-Q100 Tested and Qualiﬁed

■ Easy System Integration

Table 1. LA-ispMACH 4000V Automotive Family Selection Guide

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

Macrocells

I/O + Dedicated Inputs

Supply Voltage (V)

Pins/Package

MAX

(ns)

(MHz)

• f

• t

• Up to four global clock pins with programmable

• Up to 80 PTs per output

• Enhanced macrocells with individual clock,

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-Fit

• Fast path, SpeedLocking

• Wide input gating (36 input logic blocks) for fast

• Typical static current 10µA (4032Z)

• 1.8V core low dynamic power

• LA-ispMACH 4000Z operational down to 1.6V

• Automotive: -40 to 125°C ambient (T

• Superior solution for power sensitive consumer

• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O

• Operation with 3.3V (4000V) or 1.8V (4000Z)

clock polarity control

reset, preset and clock enable controls

path

counters, state machines and address decoders

applications

supplies

MAX

= 7.5ns propagation delay

= 168MHz maximum operating frequency

44-pin Lead-Free TQFP

48-pin Lead-Free TQFP

and reﬁt

LA-ispMACH 4032V

Path, and wide-PT

30+2/32+4

3.3V

168

7.5

4.5

)

Introduction

The high performance LA-ispMACH 4000V/Z automo-

tive family from Lattice offers a SuperFAST CPLD solu-

tion that is tested and qualiﬁed to the AEC-Q100

standard. The family is a blend of Lattice’s two most

popular architectures: the ispLSI

4A. Retaining the best of both families, the LA-ispMACH

4000V/Z architecture focuses on signiﬁcant innovations

to combine the highest performance with low power in a

ﬂexible CPLD family.

The LA-ispMACH 4000V/Z automotive family combines

high speed and low power with the ﬂexibility needed for

ease of design. With its robust Global Routing Pool and

Output Routing Pool, this family delivers excellent First-

Time-Fit, timing predictability, routing, pin-out retention

and density migration.

100-pin Lead-Free TQFP

44-pin Lead-Free TQFP

48-pin Lead-Free TQFP

LA-ispMACH 4064V

30+2/32+4/64+10

• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI

• Hot-socketing

• Open-drain capability

• Input pull-up, pull-down or bus-keeper

• Programmable output slew rate

• 3.3V PCI compatible

• IEEE 1149.1 boundary scan testable

• 3.3V/2.5V/1.8V In-System Programmable

• I/O pins with fast setup path

• Lead-free (RoHS) package

interfaces

(ISP™) using IEEE 1532 compliant interface

LA-ispMACH 4000V/Z

3.3V

168

7.5

4.5

3.3V/1.8V In-System Programmable

Automotive Family

SuperFAST High Density PLDs

100-pin Lead-Free TQFP

128-pin Lead-Free TQFP

144-pin Lead-Free TQFP

LA-ispMACH 4128V

64+10/92+4/96+4

2000 and ispMACH

Data Sheet DS1017

3.3V

128

168

7.5

4.5

DS1017_02.3

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