74LV14D,118 NXP Semiconductors, 74LV14D,118 Datasheet

IC HEX INV SCHMITT TRIG 14SOIC

74LV14D,118

Manufacturer Part Number
74LV14D,118
Description
IC HEX INV SCHMITT TRIG 14SOIC
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet

Specifications of 74LV14D,118

Number Of Circuits
6
Logic Type
Inverter with Schmitt Trigger
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Number Of Inputs
1
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LV
High Level Output Current
- 12 mA
Low Level Output Current
12 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Logical Function
Inverter Schmit Trig
Number Of Elements
6
Input Type
Schmitt Trigger
Propagation Delay Time
48ns
Operating Supply Voltage (typ)
3.3V
Package Type
SO
Operating Temp Range
-40C to 125C
Pin Count
14
Quiescent Current
40uA
Output Type
Schmitt Trigger
Technology
CMOS
Mounting
Surface Mount
Operating Temperature Classification
Automotive
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LV14D-T
74LV14D-T
935069490118
1. General description
2. Features and benefits
3. Applications
The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC14 and 74HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
hysteresis voltage V
74LV14
Hex inverting Schmitt trigger
Rev. 5 — 5 January 2011
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
Typical output ground bounce < 0.8 V at V
Typical HIGH-level output voltage (V
T
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
amb
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
= 25 C
H
.
T+
and the negative voltage V
CC
OH
) undershoot: > 2 V at V
= 2.7 V and V
CC
= 3.3 V and T
CC
= 3.6 V
T
amb
is defined as the input
= 25 C
CC
Product data sheet
= 3.3 V and

Related parts for 74LV14D,118

74LV14D,118 Summary of contents

Page 1

Hex inverting Schmitt trigger Rev. 5 — 5 January 2011 1. General description The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74LV14N 40 C to +125 C 74LV14D 40 C to +125 C 74LV14DB 40 C to +125 C 74LV14PW 40 C to +125 C 74LV14BQ 5. Functional diagram mna204 Fig 1. Logic symbol ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LV14 GND Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 6.2 Pin description Table 2. Pin description Symbol Pin GND 74LV14 Product data sheet 001aah095 Fig 5. Pin configuration DHVQFN14 Description data input data output data input data output ...

Page 4

... NXP Semiconductors 7. Functional description Table 3. Function table H = HIGH voltage level LOW voltage level. Input Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I supply current CC I additional supply current CC C input capacitance I [1] Typical values are measured at T ...

Page 6

... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions t propagation delay nA to nY; see power dissipation capacitance V I [1] All typical values are measured the same as t and PLH PHL [3] Typical values are measured at nominal supply voltage (V ...

Page 7

... NXP Semiconductors Table 8. Measurement points Supply voltage V CC < 2 3.6 V  4.5 V Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load resistance Load capacitance including jig and probe capacitance. L Fig 7. Load circuit for switching times Table 9 ...

Page 8

... NXP Semiconductors Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Symbol Parameter Conditions V negative-going V T CC threshold voltage hysteresis voltage [1] All typical values are measured at T 14. Waveforms transfer characteristics T− Fig 8. Transfer characteristic 74LV14 Product data sheet … ...

Page 9

... NXP Semiconductors (μ 0 Fig 10. Typical 74LV14 transfer characteristics Fig 12. Typical 74LV14 transfer characteristics 74LV14 Product data sheet 001aaa659 100 I CC (μA) 0.9 1.2 V (V) I Fig 11. Typical 74LV14 transfer characteristics 300 I CC (μA) 200 100 0 0 0.6 1.2 1.8 All information provided in this document is subject to legal disclaimers. Rev. 5 — ...

Page 10

... NXP Semiconductors 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula add P = additional power dissipation (W); add f = input frequency (MHz rise time (ns fall time (ns I CC(AV) Average I An example of a relaxation circuit using the 74LV14 is shown in (1) Positive-going edge ...

Page 11

... NXP Semiconductors 16. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT337-1 Fig 17. Package outline SOT337-1 (SSOP14) ...

Page 14

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 16

... NXP Semiconductors 17. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 12. Revision history Document ID Release date 74LV14 v.5 20110105 • Modifications: Table 74LV14 v ...

Page 17

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 18

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LV14 Product data sheet 19 ...

Page 19

... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Transfer characteristics ...

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