mt8885an1 Zarlink Semiconductor, mt8885an1 Datasheet
mt8885an1
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1996-2005, Zarlink Semiconductor Inc. All Rights Reserved. Integrated DTMF Transceiver with Power Down and Adaptive Micro Interface MT8885AN MT8885AP MT8885AE MT8885AN1 MT8885AE1 MT8885ANR MT8885ANR1 Description The MT8885 is a monolithic DTMF transceiver with call progress filter fabricated in CMOS technology offering low power consumption and high reliability ...
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... CMOS compatible. MT8885 VDD St/GT ESt VRef D2 7 VSS D1 8 OSC1 D0 9 OSC2 PWDN NC 11 IRQ/CP DS/RD RS0 Figure 2 - Pin Connections Description /2 Zarlink Semiconductor Inc. Data Sheet • PWDN 28 PIN PLCC ...
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... VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high impedance state. Finally, the whole device is put in a power-down state when the PWDN pin is asserted. MT8885 Description frees the device to accept a new tone pair. The TSt 3 Zarlink Semiconductor Inc. Data Sheet TSt ...
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... Provision is made for connection of a feedback resistor to the op- DD MT8885 IN+ IN VOLTAGE GAIN V Ref ( Figure 3 - Single-Ended Input Configuration MT8885 IN IN Ref INPUT IMPEDANCE diff) - R5/ diff Figure 4 - Differential Input Configuration 4 Zarlink Semiconductor Inc. Data Sheet (1/ωC) ...
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... 1633 1633 1633 LOGIC LOW, 1= LOGIC HIGH ), v reaches the threshold ( the steering logic to register the tone c GTP TSt 5 Zarlink Semiconductor Inc. Data Sheet ...
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... REC DPmax GTPmax DAmin ≤ REC DPmin GTPmin DAmax ≥ DAmax GTAmax DPmin ≤ DAmin GTAmin DPmax 6 Zarlink Semiconductor Inc. Data Sheet ) TSt - TSt is the minimum signal duration REC with a long t REC ) GTP DO ...
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... ESt a) decreasing tGTP; (tGTP < tGTA (R1C1 GTP C1 GTA (R1R2) / ( St/ ESt b) decreasing tGTA; (tGTP > tGTA) Figure 6 - Guard Time Adjustment 7 Zarlink Semiconductor Inc. Data Sheet / ( TSt / TSt / ( TSt / TSt ...
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... REC ID TONE TONE # GTP t GTA t PStRX # n t PStb3 Figure 7 - Receiver Timing Diagram -25 0 250 500 FREQUENCY (Hz) = Reject = May Accept = Accept Figure 8 - Call Progress Response 8 Zarlink Semiconductor Inc. Data Sheet TONE # TSt # ( 750 ...
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... When the divider reaches the appropriate MT8885 Figure 9 - Description of Timing Events Note that Table 1 is the same as the receiver and f LOW HIGH 9 Zarlink Semiconductor Inc. Data Sheet ) are referred to as Low Group and High ...
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... DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B description for details. MT8885 Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 10 - Spectrum Plot 10 Zarlink Semiconductor Inc. Data Sheet ...
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... The IMD .... + IMD Equation 2. THD (%) For a Dual Tone 11 Zarlink Semiconductor Inc. Data Sheet %Error +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0. and V correspond to the low group ...
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... By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated. Figure 12(b) shows the connection of these Intel processors to the MT8885 transceiver. MT8885 MT8885 MT8885 OSC1 OSC2 OSC1 OSC2 Figure 11 - Common Crystal Connection 12 Zarlink Semiconductor Inc. Data Sheet MT8885 ...
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... Read from Receive Data Register Write to Control Register Read from Status Register Table 3 - Internal Register Functions IRQ CP/DTMF Table 4 - CRA Bit Positions C/R S/D RxEN Table 5 - CRB Bit Positions 13 Zarlink Semiconductor Inc. Data Sheet Function b0 TOUT b0 BURST ENABLE ...
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... Register Select. A logic high selects control register B for the next write cycle to the control register address. After writing to control register B, the following control register write cycle will be directed to control register A. Table 6 - Control Register A Description MT8885 8031/8051/ MT8885 8080/8085 CS A8-A15 D0-D3 ALE RS0 P0 DS/RD RD R/W/WR WR Description 14 Zarlink Semiconductor Inc. Data Sheet MT8885 CS D0-D3 RS0 DS/RD R/W/WR 12 (b) Intel ...
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... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 8 - Status Register Description 15 Zarlink Semiconductor Inc. Data Sheet Status Flag Cleared Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. ...
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... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT8885 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... RS0 R Figure 14 - Application Notes 17 Zarlink Semiconductor Inc. Data Sheet Data ...
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... Typ. I 3.0 DDQ I 5.5 DDTX I 4.5 DDRX I 7 0.7 IHO 0.3 V ILO V 0.43 0.46 TSt Zarlink Semiconductor Inc. Data Sheet Min. Max. Units 6.0 V -0 -65 +150 1000 mW Units Test Conditions 5.25 V °C +85 MHz Max. Units Test Conditions µA 15.0 TOUT and RxEN bits asserted to power- down mode 9 ...
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... V SS ‡ Sym. Min. Typ. Max. I 100 PSRR 50 CMRR VOL fc 0.3 19 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions V No load load µ load kΩ Note µ µA V ...
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... Hz ±3.5% -16 -12 22 Voltages are with respect to ground (V ‡ Sym. Min. Typ. f 320 540 HR -30 20 Zarlink Semiconductor Inc. Data Sheet ° Units Test Conditions ≥ 100 kΩ LGS pp SS GS, 3 KHz Note 9 ...
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... RWS t 20 RWH Zarlink Semiconductor Inc. Data Sheet Units Conditions ms Note 11 ms Note 11 µs Figure 7, Note 9 µs Figure 7, Note 9 ms DTMF mode ms DTMF mode ms Call Progress mode ms Call Progress mode dBm R =10 kΩ ...
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... CSS t 40 CSH RDS, DSS ± 1.5% 2 Hz. ± 2%). ≥ 1000 Zarlink Semiconductor Inc. Data Sheet ), unless otherwise stated. SS Max. Units Conditions ns Figures 100 ns Figures Figures 16 Figures 16 Figures Figures Figures 16 ...
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... AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) Addr * non-mux AS.Addr * microprocessor pins Figure 16 - Motorola BUS Timing Diagram MT8885 RWS t DDR AS Addr Addr CSH High Byte of Addr t CSS 23 Zarlink Semiconductor Inc. Data Sheet t RWH t DHR Data Data t t DSW DHW ...
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... RD must be high on the falling edge of CS for Intel Bus Timing MT8885 t CSS DDR AH Data A8-A15 Address t CSH Figure 17 - Intel Read Timing Diagram t CSS DSW t AH Data A8-A15 Address t CSH Figure 18 - Intel Write Timing Diagram 24 Zarlink Semiconductor Inc. Data Sheet t DHR DHW ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...