le79555 Zarlink Semiconductor, le79555 Datasheet
le79555
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le79555 Summary of contents
Page 1
... Legerity Holdings. Subscriber Line Interface Circuit DESCRIPTION The Le79555 device, part of the Legerity VoiceEdge™ family VE580 series of devices, was designed for high-density POTS applications requiring a power saving, small footprint SLIC device. The new SLIC device fulfills today's requirements for POTS linecard markets requiring a balance of high- performance cost-effective silicon components ...
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... Application Circuits .17 Line card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Physical Dimensions .20 44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 32-Pin QFN (8x8 .21 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Revision .22 Revision .22 Revision .23 Revision .23 Revision .23 Revision .23 Revision .24 Revision .24 2 Zarlink Semiconductor Inc. ...
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... Active, Ringing, Standby, Disconnect, Reverse Polarity, and Tip Open. The Le79555 device is a low cost, high performance device providing key features required for POTS markets worldwide, including: low power dissipation and ground key detection, as well as all of the features offered currently by Legerity's Transformer SLIC family, Le7920/22 ...
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... When an off hook condition occurs, the DB pin becomes more positive than the DA pin, and the DET pin will go low to indicate an off-hook. Ring Relay Driver The ring relay driver is active only in the Ringing state. Relay Driver A relay driver is activated by logic Low at either input pin, D1, or D2. D1 controls relay driver RYOUT1; D2 controls relay driver RYOUT2. 4 Zarlink Semiconductor Inc. ...
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... CHS 4 32-Pin QFN Exposed Pad Zarlink Semiconductor Inc N N/C HPB 29 28 N/C 27 HPA 26 N/C 25 VTX 24 N/C RSVD N HPB 21 20 HPA ...
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... Exposed This must be connected to the most negative battery on the SLIC device pin side of D Pad (QFN Battery the test and application circuits. package) Description = VDC KDC 6 Zarlink Semiconductor Inc. • VAB . KDC is the VDC scale factor. shown on VBH ...
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... BGND BGND to + BAT ±10 mA –0 1.4 W 3.0 W θ JA 52°C/W typ 25° C/W typ JESD22 Class 1C compliant 7 Zarlink Semiconductor Inc 0 ° ° C. Operation above 145 C junction temper- ° –40 to +85 C 4.75 to 5.25 V –40 to – – ...
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... SPECIFICATIONS Refer to Figure 9, on page 16 for the Le79555 test circuit specifications. Transmission Performance Description Two-wire return loss Analog output (VTX) impedance Analog (VTX) output offset voltage Overload level, 2-wire Overload level THD (Total Harmonic Distortion) THD, On hook Longitudinal Capability See Figure 6 ...
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... RB to GND = 100 Ω Test Conditions (See Note 1) Min 3.4 kHz 30 = 100 MV RMS) (V RIPPLE 3.4 kHz Off-hook constant current region 28 = 500 MV PP) (V RIPPLE CAS pin BAT 9 Zarlink Semiconductor Inc. Typ Max Unit Note +0. +0. –5.92 3 –6.02 –5. +0.35 3,4 –6.02 – ...
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... RSN 200 Hz to 3.4 kHz Test Conditions (See Note 1) Test Conditions (See Note 0.3 mA OUT I = –0.1 mA OUT Test Conditions (See Note 1) Source resistance = 2 MΩ 10 Zarlink Semiconductor Inc. Min Typ Max Unit 45 70 130 190 mW 860 1200 350 400 Min Typ ...
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... IGK, Ground-key detector threshold Relay Driver Output (RINGOUT, RYOUT1, RYOUT2) Description On voltage Off leakage Zener breakover Zener On voltage = 600 Ω. Also, refer to the Le79555 device test circuit in 1. Unless otherwise noted Overload level is defined as THD = 1%. b) Overload level is defined as THD = 1.5%. 3. ...
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... D D off-hook the regulator filter capacitor and f CAS frequency. Standby loop current (resistive region). 12 Zarlink Semiconductor Inc. DET Output X X Loop detector Ring Ground (see note) Ring trip Ring trip Loop detector Loop detector is the desired 2-wire AC input impedance. When ...
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... DC1 DC2 = |BAT| − Diode Figure 3. Feed Programming A (TIP) RSN SLIC L B (RING) RDC 13 Zarlink Semiconductor Inc where − 7.2 V − /210 DC1 DC2 ...
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... BRS = 20 log Figure 6. Longitudinal Balance VTX A (TIP SLIC AGND (RING Closed, S1Open / V ) 4-L Long. Sig. Gen log Zarlink Semiconductor Inc ...
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... Figure 7. Two-Wire Return Loss A (TIP) VTX SLIC M AGND = 600 Ω (RING) RSN ) S Figure 8. RFI 200 Ω 1 200 Ω Zarlink Semiconductor Inc kΩ 180 kΩ 150 k Ω Ω A (TIP (RING) 50 Ω ...
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... Figure 9. Le79555 Engineering Test Circuit 2 (TIP 220 nF B (RING 2.2 nF RINGOUT RYOUT1 RYOUT2 N 330 nF BAT VBH 0.47 µF IN400x C C CH1 CH2 15 nF 560 1.3 kΩ C FIL 0.47 µF L Low ESR 1 1mH D CHCLK1 MUR120 DA VCC ...
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... L1 is recommended mH SR2 SR1 1.0 MΩ 330 nF R SR1 909 kΩ R SR3 1.0 M Ω SR4 SR2 909 kΩ 330 nF DA VCC Le79555 VTX A(TIP) HPA C HP HPB RSN B(RING) RDC RINGOUT RYOUT1 RYOUT2 AGND RSVD QBAT D2 D1 BGND C3 C2 VBH VBAT C1 ...
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... INT RST VIN #4 VOUT #4 CD1 #4 CD2 # CHCLK VCCA VCCD VREF AGND DGND 18 Zarlink Semiconductor Inc. +5VD kΩ 10 kΩ DXA/DU DRA/DD TSCA DXB DRB TSCB FS/FSC PCLK/DCL MCLK/E1 DCLK/S0 CS/PG DIO/S1 INT ...
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... SMT RDC2 RD 1 SMT RT 1 SMT RRX 1 SMT D , MUR 120 (D0-41) VBH 2 D DIODE CHCLK1 Coiltronics SD25-102 L1 1 Inductor U2 1 Secondary Protector U1 1 Le79555 U4 1 Le58QL063 OUT 3 Capacitor (X7R) C REF RPA, RPB 2 SMT SMT SR2 SR3 SMT SR4 SR1 ...
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... The top of package is smaller than the bottom of the package by 0.15mm. 12. This outline conforms to Jedec publication 95 registration MS-026 13. The 160 lead is a compliant depopulation of the 176 lead MS-026 variation BGA. 44-Pin TQFP 20 Zarlink Semiconductor Inc. ...
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... The Terminal #1 identifier may be either a mold or marked feature. 5.90 5. Coplanarity applies to the exposed pad as well as the terminals. 6. Reference Document: JEDEC MO-220. 0.63 7. Lead width deviates from the JEDEC MO-220 standard. 0.05 32-Pin QFN 21 Zarlink Semiconductor Inc degrees. ...
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... Thermal data for 32-pin QFN package • Added a note regarding maximum power dissipation values under the Absolute Maximum Ratings table Standby state test conditions, changed the equation Long Loops, Active State; KDC ( Zarlink Semiconductor Inc Accuracy); VAB, Open Circuit voltage in DC ...
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... Modified Longitudinal Balance graphic – Modified Two-Wire Return Loss graphic (changed CT1 from 120 pF to 180 pF) – Modified RFI graphic – Modified Le79555 test circuit graphic • Modified Application Circuit graphic • Added Note 2 to "Application Circuit" section • Updated Linecard Parts List to reflect the updated application circuit Revision • ...
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... Revision Application Circuits, • Modified on page 17 Line card Parts List, • Modified on page 19 Revision • Enhanced format of package drawings in • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 Physical Dimensions, on page 20 24 Zarlink Semiconductor Inc. ...
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... I C Standard Specification as defined by Philips. Zarlink, ZL, the Zarlink Semiconductor logo are trademarks, and Legerity, the Legerity logo and combinations thereof are registered trademarks of Zarlink Semiconductor Inc. All other trademarks and registered trademarks are the property of their respective owners. © 2007 Zarlink Semiconductor Inc. All Rights Reserved. ...