mt8986al1 Zarlink Semiconductor, mt8986al1 Datasheet - Page 14

• Manufacturer Part Number: mt8986al1
• Description: Multiple Rate Digital Switch
• Manufacturer: Zarlink Semiconductor

Initialization of the MT8986
On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially
hazardous condition when multiple MT8986 ST-BUS outputs are tied together to form matrices, as these outputs
may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the matrices, and put all other channels into the high impedance state. Care should be taken that no two
ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the
matrices can bring the ODE signal high to relinquish high impedance state control to the CMH
BIT
4-3
2-0
7
6
5
Identical
2 Mb/s *
2 Mb/s
Rate
I/O
STA2-0
NAME
MS1-0
STA3
ME
SM
# of Input x
Streams
Output
4x4 *
8x8
Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the
Connection Memory Low, except when the Control Register is accessed again. When 0, the
Memory Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
Message Enable. When 1, the contents of the Connection Memory Low are output on the Serial
Output streams except when in High Impedance as set by the ODE input. When 0, the Connection
Memory bits for each channel determine what is output.
Stream Address Bit 3. This bit is used in the 44 pin packages when 16 x 8 switching configuration
is selected. It is used with STA2-0 to select one of the 16 input data streams whenever the Data
Memory is to be read. The programming of this bit has no effect in other switching configurations.
Memory Select Bits. The memory select bits operate as follows:
The number expressed in binary notation on these bits refers to the input or output ST-BUS stream
which corresponds to the subsection of memory made accessible for subsequent operations.
The use of these bits depends on the switching configuration as well as the device’s main operation
defined by the DMO bit of the Interface Mode Selection register. Tables 6 and 7 show the
utilization of these bits according to the device’s main operation.
SM
1-0 - Connection Memory Low
7
0-0 - Not to be used
1-1 - Connection Memory High
0-1 - Data Memory (read only from the CPU)
STA2, STA1, STA0
STA1, STA0
select subsections of
STA bits used to
ME
Figure 3 - Control Register Description
6
Control Register - Read/Write
Memory
the Data
STA3
5
Zarlink Semiconductor Inc.
MT8986
MS1
4
14
STA2, STA1, STA0
STA1, STA0
MS0
select subsections of
3
DESCRIPTION
STA bits used to
the Connection
Memory
STA2
2
STA1
1
STA0
A4, A3, A2, A1, A0
A4, A3, A2, A1, A0
0
within the selected subsection
select individual Connection
and Data Memory positions
Input Address pins used to
b
0s.
Data Sheet