zl30102 Zarlink Semiconductor, zl30102 Datasheet - Page 12

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zl30102

Manufacturer Part Number
zl30102
Description
T1/e1 Stratum 4/4e Redundant System Clock Synchronizer For Ds1/e1 And H.110
Manufacturer
Zarlink Semiconductor
Datasheet

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Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the
reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency
failures must be absent for 10 s to let the timer re-qualify the input reference signal as valid. Multiple failures of less
than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure
4 where REF0 experiences disruptions while REF1 is stable.
REF0 /
REF1 /
REF2
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz or 16.384 MHz and provides this information to the
various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the selected accuracy range, see Table 1.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Reference Frequency
Precise Frequency
Coarse Frequency
Single Cycle
Detector
Monitor
Monitor
Monitor
Figure 3 - Reference Monitor Circuit
OR
Zarlink Semiconductor Inc.
ZL30102
REF_OOR = reference out of range.
REF_DIS= reference disrupted.
Both are internal signals.
dis/re-qualify
12
timer
OR
OR
REF_OOR
REF_DIS
Reference
select
state machine
Mode select
state machine
Data Sheet
REF_SEL1:0
HOLDOVER
REF_FAIL0 /
REF_FAIL1 /
REF_FAIL2

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