zl30101 Zarlink Semiconductor, zl30101 Datasheet - Page 11

• Manufacturer Part Number: zl30101
• Description: T1/e1 Stratum 3 System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
3.0
The ZL30101 is a DS1/E1 Stratum 3 System Synchronizer providing timing (clock) and synchronization (frame)
signals to interface circuits for DS1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block
diagram which is described in the following sections.
3.1
The ZL30101 accepts two simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE
corrector circuit based on the reference selection (REF_SEL) input.
3.2
The input references are monitored by two independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be
observed.
Pin #
59
60
61
62
63
64
•
•
•
•
Reference Select Multiplexer (MUX)
Reference Monitor
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz and provides this information to the
various monitor circuits and the phase detector circuit of the DPLL.
Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock
is within the applicable accuracy range of ±12 ppm, see Figure 5. It will take the precise frequency monitor
up to 10 s to qualify or disqualify the input reference.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large
phase hits or the complete loss of the clock.
Functional Description
TIE_CLR
BW_SEL
Name
V
NC
IC
IC
DD
Internal Connection. Connect this pin to ground.
Internal Connection. Connect this pin to ground.
Positive Supply Voltage. +3.3 V
No internal bonding Connection. Leave unconnected.
TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time Interval
Error (TIE) correction circuit resulting in a realignment of the input phase with the output
phase.
Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loop
filter, see Table 1 on page 18. Set continuously high to track jitter on the input reference
closely or temporarily high to allow the ZL30101 to quickly lock to the input reference.
Zarlink Semiconductor Inc.
ZL30101
11
DC
nominal.
Description
Data Sheet