zl30116 Zarlink Semiconductor, zl30116 Datasheet
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zl30116 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2008, Zarlink Semiconductor Inc. All Rights Reserved. OC-48/OC-192 System Synchronizer an email to ZL30116GGGV2 100 Pin CABGA ZL30116GGG2V2100 Pin CABGA* *Pb Free Tin/Silver/Copper • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • ...
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... Applications TM • AdvancedTCA Systems • Multi-Service Edge Switches or Routers • Multi-Service Provisioning Platforms (MSPPs) • Add-Drop Multiplexers (ADMs) • Wireless/Wireline Gateways • Wireless Base Stations • DSLAM / Next Gen DLC • Core Routers ZL30116 2 Zarlink Semiconductor Inc. Data Sheet ...
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... DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ZL30116 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8 - Typical Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 - External Feedback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ZL30116 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ZL30116 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... The following table captures the changes from the December 2005 issue. Page 12 1.1, “DPLL Features“ 14 Table 2 ZL30116 Item Updated new ordering part numbers. Correct chip id_reg number. Item Changed the naming and description of the frame pulse delay offset registers to clearly show that they form a 22-bit register spread out over 3 8-bit registers ...
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... The default frequency for this output is 2.048 MHz. K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p0_clk0 frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this output is 8.192 MHz. ZL30116 Description ss. 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Master/Slave control (LVCMOS, Schmitt Trigger). This pin selects the mode of u operation for the device. If set high, slave mode is selected. If set low, master mode is selected. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. ZL30116 Description 8 Zarlink Semiconductor Inc. Data Sheet ...
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... This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. ZL30116 Description 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Positive Supply Voltage. +1.8V CORE Positive Analog Supply Voltage. +3. C10 Positive Analog Supply Voltage. +1.8V CORE ZL30116 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet . If this pin is not used DD ...
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... Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30116 Description 11 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. ...
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... The input references are continuously monitored for frequency accuracy and phase regularity least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30116 will enter in the Normal (locked) mode. ZL30116 ...
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... Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz are also available. 1.544 MHz 2.048 MHz 8.192 MHz Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies ZL30116 DPLL2 DPLL1 Figure 3 - Reference and Sync Inputs 2 kHz 16.384 MHz 8 kHz 19 ...
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... Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in Table 3. Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies ZL30116 input is selected with its corresponding ref n ref ...
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... When there are no CFM or SCM failures, the accumulator decrements until it reaches its lower threshold during the qualification window. ref upper threshold lower threshold t d gst_fail Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures ZL30116 CFM or SCM failures disqualification time qualification time = ...
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... Output Clocks and Frame Pulses The ZL30116 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n, diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks, and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available ...
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... MHz 51.84 MHz 622.08 MHz 77.76 MHz Table 4 - Output Clock and Frame Pulse Frequencies 1. M= -128 to 127 defined as an 8-bit two’s complement value. +ve values divide, -ve values multiply 9270 selects 2 kH ZL30116 p0_clk0, p1_clk0 p0_clk1, p1_clk1 (LVCMOS) (LVCMOS) 2 kHz p ...
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... Configurable Input-to-Output and Output-to-Output Delays The ZL30116 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15 ...
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... One method of connecting two ZL30116 devices in a master/slave configuration is shown in Figure 8 where there is a dedicated crossover link between timing cards. Any of the master’s unused outputs and the slave’s unused inputs can be used as a crossover link ...
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... In addition to the static delay compensation described in the “External Feedback Inputs” section on page 21, the ZL30116 also provides the option of dynamic delay compensation to minimize path delay variation associated with external clock drivers and long PCB traces. This is accomplished by re-directing the internal DPLL1 feedback path to external pins and closing the loop externally as shown in Figure 9 ...
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... Software Configuration The ZL30116 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor can operate in a manual mode where the system processor controls most of the operation of the device ...
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... ZL30116 Reset Value Description (Hex) FF Control register to mask each failure indicator for ref6 and ref7 Reference Monitor Setup FF Ref0 and ref1 auto-detected frequency value status register FF Ref2 and ref3 auto-detected frequency value status register ...
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... ZL30116 Reset Value Description (Hex) See Control register for the DPLL1 mode of operation Register Description 00 DPLL1 reference selection or reference selection status 3C Control register to mask each failure indicator (SCM, CFM, PFM and GST) used for automatic ...
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... ZL30116 Reset Value Description (Hex) 10 Control register for the ref0 and ref1 priority values 32 Control register for the ref2 and ref3 priority values 54 Control register for the ref4 and re5 priority values 76 Control register for the ref6 and ref7 priority ...
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... ZL30116 Reset Value Description (Hex) 11 Control register to select fp1 type 00 Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262.144 MHz 00 Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/262.144 MHz 00 Bits [21:16] of the programmable frame pulse ...
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... ZL30116 Reset Value Description (Hex) 05 Control register to select the sdh_fp0 frame pulse frequency 23 Control register to select fp0 type 00 Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz 00 Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311 ...
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... ZL30116 Reset Value Description (Hex) 00 Control register for the [13:8] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. 00 Control register for the custom configuration A: single cycle SCM low limiter 00 Control register for the custom configuration ...
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... Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30116 Reset Value Description (Hex) 00 Control register for the custom configuration B: The [7:0] bits of the single cycle CFM high limiter. 00 Control register for the custom configuration B: The [15:0] bits of the single cycle CFM high limiter ...