zl30461 Zarlink Semiconductor, zl30461 Datasheet
zl30461
Related parts for zl30461
zl30461 Summary of contents
Page 1
... Copyright 2004, 2003, Zarlink Semiconductor Inc. All Rights Reserved. Compact Stratum 3 Timing Module ZL30461MGG Applications • SONET/SDH Add/Drop multiplexers • SONET/SDH up-links • ATM edge switches • Line cards Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30461 Data Sheet December 2003 Ordering Information 240 BGA 0qC to +70qC ...
Page 2
... The ZL30461 is a Compact Timing Module, which functions as a complete system clock solution for general Stratum 3 and SONET/SDH timing applications. The ZL30461 uses Zarlink's Digital and Analog Phase Locked Loop (DPLL and APLL) technology and can lock input frequencies automatically. The module has multiple output clocks ranging from 8 kHz to 155.52 MHz, its primary output at 77 ...
Page 3
... JA77OE JA77P/N Output Enable (Input). Logic 1 on this input will enable the JA77P/N output clock and logic 0 will disable this it. (Note 1) U5 JA19Mo JA 19.44 MHz Clock (Output). This output provides a low jitter 19.44 MHz clock. ZL30461 Description . DD1 3 Zarlink Semiconductor Inc. Data Sheet ...
Page 4
... E3/DS3 pin selects a 44.736 MHz clock on C34/C44 output and logic 1 selects 34.368 MHz clock. When the E3DS3/OC3 pin is set to logic 0, a logic 0 on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and logic 1 selects 8.592 MHz clock. ZL30461 Description 4 Zarlink Semiconductor Inc. ...
Page 5
... Ground J5 G13 - G16, AGND2 Ground H13 - H16, J13 - J16, K13 - K16, L13 - L16, M13 - M16 N14, N16 P14, P16 R16, T12, T13, T15, U12, U13, U15, U17 ZL30461 Description , TGND and OSCo pins should be left DD 5 Zarlink Semiconductor Inc. Data Sheet ...
Page 6
... Data tolerant three-state I/O). Data input/output for the microprocessor port ( Data tolerant three-state I/O). Data input/output for the microprocessor port ( Data tolerant three-state I/O). Data input/output for the microprocessor port (D0 - D7). ZL30461 Description 6 Zarlink Semiconductor Inc. Data Sheet ...
Page 7
... IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test instructions and data. This pin is internally pulled unconnected. Note 1: Connections relate to the Analog PLL stage, if the jitter attenuated outputs are not being used, you do not need to make these connections. ZL30461 Description . not used, this pin should be left DD1 7 Zarlink Semiconductor Inc ...
Page 8
... Control Bits 2.2.2 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.3 ZL30461 Register Map 2.2.4 Register Description 3.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1 ZL30461 Mode Switching - Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.1 System Start-Up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 31 3.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . 31 3.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER --> HOLDOVER --> NORMAL . . . . 32 3.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 33 3 ...
Page 9
... Figure 2 - 240 Pin BGA Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - LVPECL Output Termination Circuit Figure 4 - C155o and C34/C44 Clock Generation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5 - ZL30461 State Machine Figure 6 - Hardware and Software Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7 - Transition from Free-Run to Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 8 - Automatic Entry into Auto Holdover State and Recovery into Normal Mode . . . . . . . . . . . . . . . . . . . . . 32 Figure 9 - Entry into Auto Holdover State and Recovery into Normal Mode by Switching References ...
Page 10
... Table 1 - Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Operating Modes and States Table 3 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5 - ZL30461 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6 - Control Register 1 (R/ Table 7 - Status Register 1 ( Table 8 - Control Register 2 (R/ Table 9 - Phase Offset Register 2 (R/ Table 10 - Phase Offset Register 1 (R/ Table 11 - Device ID Register (R) ...
Page 11
... Acquisition and Core PLLs without changing the transfer function of the Core PLL. 1.2 Core PLL The most critical element of the ZL30461 is the Core PLL. This generates a phase-locked clock, filters jitter and wander and suppresses input phase transients. All of these features are in agreement with international standards: • ...
Page 12
... Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference If the ZL30461 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the ...
Page 13
... Using RefAlign with an 8 kHz Reference If the ZL30461 is locked kHz reference, then the output clocks can be brought into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the procedures below: For 0.1 Hz filtering applications (FCS=1, FCS2=0) • ...
Page 14
... After initiating a reference realignment the ZL30461 will enter Holdover Mode for 200 ns while aligning the internal clocks to remove the static phase error. The ZL30461 will then begin the normal locking procedure. The LOCK pin will remain high during the realignment process. ...
Page 15
... ZL30461 Output Driver LVPECL Driver Note : Vcc = +3.3V Figure 3 - LVPECL Output Termination Circuit 1.4.3 Clock Formats The ZL30461 outputs the following clock and frame pulses: • C1.5o: 1.544 MHz clock with nominal 50% duty cycle • C2o: 2.048 MHz clock with nominal 50% duty cycle • ...
Page 16
... Requirements for clock modes are defined in the international standards e.g.: G.812, G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators. The ZL30461 supports all clock modes and each of these modes have a corresponding state in the Control State Machine. ...
Page 17
... The Reset state is entered by pulling the RESET pin to logic 0 for a minimum of 1 µs. When the RESET pin is pulled back to logic 1, internal logic starts a 625 µs initialization process before switching into the Free-run state (MS2, MS1 = 10 recommended to perform a module reset immediately after power up, to ensure the ZL30461 is set to a know state. ...
Page 18
... Both of them force the Core PLL to transition into and out of the Auto Holdover state. The ZL30461 State Machine may also be driven by controlling the mode select pins or bits MS2, MS1. In order to avoid network synchronization problems, the State Machine has built-in basic protection that does not allow switching the Core PLL into a state where it cannot operate correctly e ...
Page 19
... Microprocessor Interface The ZL30461 DPLL can be controlled by a device connected directly to the hardware control pins. If the HW pin is tied to logic 0 (see Figure 6 “Hardware and Software Control options”), a microprocessor with a Motorola type bus may be used to control PLL operation and check its status. Under software control, the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits ...
Page 20
... Hardware and Software Control The ZL30461 offers Hardware and Software Control options that simplify design of basic or complex clock synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing cards without extensive programming. The complete set of control and status functions for each mode are shown in Figure 6 “ ...
Page 21
... Control Pins The ZL30461 has six dedicated control pins for selecting modes of operation and activating different functions. These pins are listed below: MS2 and MS1 pins: Mode Select. The MS2 and MS1 inputs select the PLL mode of operation. See Table 2 for details ...
Page 22
... Auto Holdover Mode: AHRD and MHR (Table 15: Core PLL Control Register). In addition to the Control bits shown in Figure 6 “Hardware and Software Control Options”, the ZL30461 has a number of bits and registers that are accessed infrequently or during configuration only e.g. Phase Offset Adjustment or Master Clock Frequency Calibration ...
Page 23
... Calibration Register - Byte 2 Master Clock Frequency 43 Calibration Register - Byte 1 Table 5 - ZL30461 Register Map (continued) Note: The ZL30461 uses address space from Fh. Registers at address locations not listed above must not be written or read. 2.2.4 Register Description Address Bit Name Reference Select. A zero selects the PRI (Primary) reference source as the ...
Page 24
... FLIM accuracy of the 20 MHz master oscillator input OSCi). This bit may change state momentarily in the event of large jitter or wander excursions occurring when the input reference is close to the frequency limit range. ZL30461 Functional Description Normal Mode (Locked Mode) Holdover Mode Free-run Mode ...
Page 25
... For example: from a current position of 22H, four writes are required to advance the clocks by 244 ns: write 23H, 24H, 25H, 26H. Writing numbers in reverse order will delay clocks from their present position. ZL30461 Functional Description Functional Description Table 8 - Control Register 2 (R/W) ...
Page 26
... See the Phase Offset Register 2 for details. C16POA0 Address Bit Name Device Identification Number. These four bits represent the device part number. The 7-4 ID7 - 4 ID number for ZL30461 is 0111. 3-0 ID3 - 0 Device Revision Number. These bits represent the revision number, starts from 0000. Address Bit Name 7 RSV Reserved ...
Page 27
... C6o (6.312 MHz) Clock Disable. When set to 1, this bit tristates the 6.312 MHz 1 C6odis clock output. C19o (19.44 MHz) Clock Disable. When set to 1, this bit tristates the 0 C19odis 19.44 MHz clock output. Table 14 - Clock Disable Register 2 (R/W) ZL30461 Functional Description Functional Description 27 Zarlink Semiconductor Inc. Data Sheet Default 00 0 ...
Page 28
... Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays all clocks Table 16 - Fine Phase Offset Register (R/W) ZL30461 Functional Description Functional Description 28 Zarlink Semiconductor Inc. ...
Page 29
... Secondary Acquisition PLL Frequency Limit. This bit goes to 1 whenever the 0 SAFL Acquisition PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large excursion of still tolerable input jitter. Table 18 - Secondary Acquisition PLL Status Register (R) ZL30461 Functional Description Functional Description 29 Zarlink Semiconductor Inc. Data Sheet ...
Page 30
... ZL30461 Mode Switching - Examples The ZL30461 is designed to transition from one mode to the other driven by the internal State Machine or by manual control. The following examples present a couple of typical scenarios of how the ZL30461 can be employed in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers). ...
Page 31
... ZL30461 will transition briefly into Holdover state to acquire synchronization and switch automatically to Normal state. If the reference clock is not available, the ZL30461 will stay in Holdover state indefinitely. Whilst in Holdover state, the Core PLL will continue generating clocks with the same accuracy as in the Free-run Mode, waiting for a valid reference clock ...
Page 32
... The failure conditions triggering this transition were described in Section 3.1.2. When in the Auto Holdover state, the ZL30461 can return to Normal state automatically if the lost reference is restored and the ADHR bit is set the reference clock failure persists for a period of time that exceeds the system design limit, the system control processor may initiate a reference switch ...
Page 33
... A reference clock is available but its frequency drifts beyond some specified limit Network Element with Stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than ±12 ppm beyond its nominal frequency. The ZL30461 indicates this condition by setting PRIOR or SECOR status bits and pins to logic 1. ...
Page 34
... When the Master Timing card fails unexpectedly, (this failure is not related to reference failure), then all Line Cards will detect this failure and they will switch to the timing supplied by the Slave Timing Card. At this moment the ZL30461 on the Slave Timing Card must be switched from the same loop filter characteristic (e.g. 1.5 Hz filter for SDH networks) as the Master Timing Card. ...
Page 35
... ZL30461 SE C Timing Card (Active Slave) Figure 11 - Block Diagram of the Master/Slave Timing Protection Switching A detailed description of this Master/Slave redundant timing architecture based on ZL30461 can be found in Application Note ZLAN-67 “Applications of the ZL30461 Master/Slave Application”. 3.3 Programming Master Clock Oscillator Frequency Calibration Register The Master Crystal Oscillator and its programmable Master Clock Frequency Calibration register (see Table 19, Table 20, Table 21, and Table 22) have been described in Section 1.6 “ ...
Page 36
... Low-level input voltage 5 Input leakage current 6 High-level output voltage 7 Low-level output voltage LVDS: Differential output 8 voltage LVDS: Change in VOD between 9 complementary output states 10 LVDS: Offset voltage LVDS: Output short circuit 11 current ZL30461 Symbol Symbol Min 3.135 DD TV ...
Page 37
... Note 2: Rise and fall times are measured at 20% and 80% levels. AC Electrical Characteristics* Parameter 1 I/P Frequency Range 2 O/P Frequency Range 3 Reference Rejection 4 Reference Pull-in 5 Reference Hold-in 6 Reference Settling Time 7 Jitter Tolerance 8 Wander Tolerance 9 Phase Transient Tolerance ZL30461 Symbol Min. Typ. Max. T 260 900 480 600 720 -0 ...
Page 38
... Lock Time 22 Tuning Alarm * Voltages are with respect to ground (GND) unless otherwise stated. Note 3: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. Note 4: Various outputs from 8 kHz to 155.52 MHz. Note 5: With reference to the Free-Run accuracy. ZL30461 Symbol Min. Max. Units ...
Page 39
... AC Electrical Characteristics - Timing Parameter Measurements - CMOS Voltage Levels* Characteristics 1 Threshold voltage 2 Rise and fall threshold voltage High 3 Rise and fall threshold voltage Low All Signals T IF Figure 12 - Timing Parameters Measurement Voltage Levels ZL30461 Symbol Timing Reference Points 39 Zarlink Semiconductor Inc. Data Sheet Typical Units V 0.5V V ...
Page 40
... Address hold 9 Data read delay 10 Data read hold 11 Data write setup 12 Data write hold t DSH R/W t ADS -D7 READ D0 -D7 WRITE ZL30461 Symbol Min. Max DSL t 100 DSH t 0 CSS t 0 CSH t 20 RWS t 5 RWH t 10 ...
Page 41
... C2o pulse width low 13 F8o to C2o delay ____ F16o tc = 125µs ____ C16o tc = 61.04ns F8o tc = 125µs C8o tc = 122.07ns ___ F0o tc = 125µs t C4L ___ C4o tc = 244.14ns C2o tc = 488.28ns ZL30461 Symbol Min F16L t 27 F16D t 26 C16L t -3 C16D t 119 F8H t 56 C8L t -3 ...
Page 42
... C19o tc = 51.44ns Figure 15 - DS1, DS2 and C19o Clock Timing AC Electrical Characteristics - C155o and C19o Clock Timing* Characteristics 1 C155o pulse width low 2 C1550 to C19o rising edge delay 3 C155o to C19o falling edge delay ZL30461 Symbol Min. Max C6L t -4 C6D t 320 328 C1 ...
Page 43
... MHz ref pulse width high 6 2.048 MHz ref input to F8o delay 7 19.44 MHz ref pulse width high 8 19.44 MHz to F8o input delay 9 19.44 MHz ref input to C19o delay 10 Reference input rise and fall time ZL30461 t t C19DLH C19DHL T Voltage Levels Figure 16 - C155o and C19o Timing Symbol Min. Max. ...
Page 44
... Figure 17 - Input Reference to Output Clock Phase Alignment AC Electrical Characteristics - Input Control Timing* Characteristics 1 Input control setup time 2 Input control hold time F8o MS1, MS2 RSEL Figure 18 - Input Control Signal Setup and Hold Time ZL30461 Symbol Min. Max. t 100 S t 100 ...
Page 45
... Performance Characteristics - Mode Switching* Characteristics 1 Core PLL Holdover accuracy 2 Holdover stability 3 Frequency limit range (LOCK pin and FLIM bit) 4 Capture range (TRUELOCK bit) 5 Reference Acceptance Threshold Lock time Filter ZL30461 Symbol Min. Max C44H t 5 C11H t 13 C34H ...
Page 46
... Switching from Normal Mode to Holdover Mode 11 Switching from Holdover Mode to Normal Mode Output Phase Slope 12 0.1 Hz Filter 13 1.5 Hz Filter Filter Filter Note 6: The phase slope is less than 7.5 ppm if the step in phase is less than 120 ns. ZL30461 Typical Units ...
Page 47
... UI 161 91.68 PP 7.06 C19o Clock Output 0.15 UI 0.964 0.886 PP 0.146 0.1 UI 0.643 0.909 PP 0.01 UI 0.064 0.149 RMS 1.5 UI 9.645 0.973 PP 0.151 47 Zarlink Semiconductor Inc. Data Sheet ZL30461 Jitter Generation Performance Units Notes C155o Clock Output ns P-P ns RMS ns P-P ns RMS ns P-P ns RMS ps P-P ps RMS ps P-P ps RMS ns P-P ns ...
Page 48
... Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30461 ZL30461 Jitter Generation Performance Equivalent Limit in limit in TYP UI time domain 0.07 UI 45.3 0.922 PP 0.5 UI 324 1.45 PP ZL30461 Jitter Generation Performance Equivalent Limit in limit in TYP UI time domain 0.05 UI 7.92 1.96 PP Equivalent Limit in limit in TYP UI time domain ...
Page 49
... Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30461 Equivalent Limit in limit in TYP UI time domain C16o, C8, C4 and C2 Clock Outputs 0.05 UI 24.4 1.26 PP Equivalent Limit in limit in TYP UI time domain 0.05 UI 1.45 1. Zarlink Semiconductor Inc. Data Sheet ZL30461 Jitter Generation Performance Units Notes ns P-P ZL30461 Jitter Generation Performance Units Notes C34 Clock Outputs ns P-P ...
Page 50
... PP 14 0.1 UI 0.643 0.866 PP 0.146 0.5 UI 3.215 0.973 PP 0.151 C16o, C8o, C4o and C2o Clock Output 0.05 UI 24.4 1. Zarlink Semiconductor Inc. Data Sheet ZL30461 Jitter Generation Performance Units Notes C155o Clock Output ns P-P ns RMS ns P-P ns RMS JA77P/N Clock Output ps P-P ps RMS ps P-P ps RMS ...
Page 51
... C155o Clock Output 0.1 UI 0.643 0.508 PP 0.058 JA77P/N Clock Output 0.1 UI 161 34.9 PP 2.8 JA19Mo Clock Output 0.1 UI 161 91.68 PP 7.06 0.1 UI 0.643 0.500 PP 0.071 51 Zarlink Semiconductor Inc. Data Sheet ZL30461 Jitter Generation Performance Units Notes ns P-P ns RMS ps P-P ps RMS ps P-P ps RMS C19o Clock Output ns P-P ns RMS ...
Page 52
... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE ACN DATE APPRD. DIMENSION Package Code Previous package codes ...
Page 53
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...