mt9094apr1 Zarlink Semiconductor, mt9094apr1 Datasheet
mt9094apr1
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mt9094apr1 Summary of contents
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... ISO -CMOS ST-BUS Digital Telephone (DPhone-II) MT9094AP MT9094APR MT9094AP1 MT9094APR1 Description The MT9094 DPhone- fully featured integrated digital telephone circuit. Voice band signals are converted to digital PCM and vice versa by a switched capacitor Filter/Codec. The Filter/Codec uses an ingenious differential architecture to achieve low noise operation over a wide dynamic range with a single 5 V supply ...
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... PIN PLCC Figure 2 - Pin Connections Description /2) volts is available at this pin for biasing external amplifiers. Connect 0 for normal operation Zarlink Semiconductor Inc. Data Sheet SPKR+ SPKR- HSPKR+ HSPKR- VDD BP S12 S11 S10 S9 S8 /2)-1.5] volts. Used internally. Connect 0.1 µF ...
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... The Functional Block Diagram of Figure 1 depicts the main operations performed within the DPhone-II. Each of these functional blocks will be described in the sections to follow. This overview will describe some of the end-user features which may be implemented as a direct result of the level of integration found within the DPhone-II. MT9094 Description for normal operation Zarlink Semiconductor Inc. Data Sheet ...
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... DSP section and provide an overall path gain resolution of 0.5 dB. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver so that a dead sounding handset is not encountered. Figure 3 depicts the nominal half-channel and side-tone gains for the DPhone-II. MT9094 4 Zarlink Semiconductor Inc. Data Sheet ...
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... ANALOG DOMAIN Figure 3 - Audio Gain Partitioning Bias may only be used internally, a 0.1 µF capacitor from the V Ref 5 Zarlink Semiconductor Inc. Data Sheet Handset Receiver (150Ω) µ-Law –6 Α-Law –3.7 dB HSPKR+ ...
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... Power up reset program MT9094 and V pins are situated on adjacent pins. Ref Bias -STG (address 0Bh -TxFG and RxFG 0 2 -STG control bits located in the FCODEC Gain Control Register Zarlink Semiconductor Inc. Data Sheet -RxFG control bits respectively ...
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... AUTO in the Receive Gain Control Register, address 1Dh) offsets are reduced to within ±one bit of zero. Autonulling circuitry was essential in the first generations of Filter/Codecs to remove the large DC offsets found in the linear technology. Newer technology has made nulling circuitry optional as offered in the DPhone-II. MT9094 7 Zarlink Semiconductor Inc. Data Sheet EN and CH EN ...
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... Actual COEF (Hz) Frequency 697 59h 695.3 770 63h 773.4 852 6Dh 851.6 941 79h 945.3 1209 9Bh 1210.9 1336 ABh 1335.9 1477 BDh 1476.6 1633 D1h 1632.8 Table 1 COEFF = 8000/Frequency (Hz) 8 Zarlink Semiconductor Inc. Data Sheet % Deviation -.20% +.40% -.05% +.46% +.20% .00% -.03% -.01% ...
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... A-Law). Control of this gain is provided by the MICA/u control bit (General Control Register, address 0Fh). This gain adjustment is in addition to the programmable gain provided by the transmit filter and DSP. MT9094 Tone duration (warble frequency in Hz) = 500/COEFF 9 Zarlink Semiconductor Inc. Data Sheet ...
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... This microport consists of three pins; a half-duplex transmit/receive data pin (DATA1), a chip select pin (CS) and a synchronous data clock pin (SCLK). MT9094 EN (see ST-BUS/Timing Control Ω 1000 pF 150 ohm (speaker) 75 Ω 1000 pF ground Figure 4 - Handset Speaker Driver ) are used in conjunction with 12 segment control bits Zarlink Semiconductor Inc. Data Sheet load ...
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... A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: ST-BUS/Timing Control A serial link is required for the transport of data between the DPhone-II and the external digital transmission device. The DPhone-II utilizes the ST-BUS architecture defined by Zarlink Semiconductor. Refer to Zarlink Application Note MT9094 (5) DATA INPUT/OUTPUT ...
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... New Call tone (0, -8, -16, -24 dB). The NCT gain bits (NCTG 2 (address 0Bh). MT9094 En -Ch En residing in the Timing Control Register and and Ch EN are enabled, default is to channel -NCTG ) reside in the FCODEC Gain Control Register Zarlink Semiconductor Inc. Data Sheet EN) are used to enable the 3 EN and 2 ...
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... B1-channel B2-channel Not Used Channels Figure 6 - ST-BUS Channel Assignment WRITE RESERVED RESERVED RESERVED RESERVED RESERVED 13 Zarlink Semiconductor Inc. Data Sheet , for operation READ RESERVED VERIFY VERIFY RESERVED RESERVED VERIFY VERIFY RESERVED NOT USED VERIFY VERIFY ...
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... EN -Ch EN must also be set LBoi Setting this bit causes data on DSTo to be looped back to DSTi directly at the pins. MT9094 WRITE RESERVED RESERVED RESERVED RESERVED 14 Zarlink Semiconductor Inc. Data Sheet READ VERIFY VERIFY RESERVED VERIFY VERIFY RESERVED VERIFY VERIFY RESERVED VERIFY ...
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... NCTG NCTG 1 0 Setting (dB (default) OFF 0 1 -9. -6. -3.32 0 3.32 6.64 9.96 15 Zarlink Semiconductor Inc. Data Sheet ADDRESSES 00h and 09h are RESERVED ADDRESS = 0Ah WRITE/READ VERIFY Power Reset Value X000 X000 TxFG 0 0 TxFG TxFG TxFG ...
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... µ CCITT µ µ -Law (de)coding is selected. 16 Zarlink Semiconductor Inc. Data Sheet ADDRESSES 0Ch and 0Dh are RESERVED ADDRESS = 0Eh WRITE/READ VERIFY Power Reset Value HSSPKR 0000 0000 ADDRESS = 0Fh WRITE/READ VERIFY Power Reset Value NCT 0000 0000 EN µ ...
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... Zarlink Semiconductor Inc. Data Sheet ADDRESS = 11h WRITE Power Reset Value XXX0 1010 ADDRESS = 12h WRITE/READ VERIFY Power Reset Value 0000 0000 ADDRESS = 13h WRITE/READ VERIFY Power Reset Value XXXX 0000 ...
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... EN and Ch EN are enabled, data defaults to channel ADDRESS = 16h WRITE/READ VERIFY - - - - - Zarlink Semiconductor Inc. Data Sheet Power Reset Value XX0X 0000 EN and Power Reset Value X00X XXXX ADDRESSES 17h - 1Ch are RESERVED ...
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... ADDRESS = 1Dh WRITE/READ VERIFY Gain Setting (dB) B5-B0 +22.5 1F +21.0 1E +19.5 1D +18.0 1C +16.5 1B +15.0 1A +13.5 19 +12.0 18 +10.5 17 +9.0 16 +7.5 15 +6.0 14 +4.5 13 +3.0 12 +1.5 11 +0.0 10 -1.5 0F -3.0 0E -4.5 0D -6.0 0C -7.5 0B -9.0 0A -10.5 09 -12.0 08 -13.5 07 -15.0 06 -16.5 05 -18.0 04 -19.5 03 -21.0 02 -22.5 01 -24 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 B0 0 Gain Setting (dB) -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 -48.0 -49.5 -51.0 -52.5 -54.0 -55.5 -57.0 -58.5 -60.0 -61.5 -63.0 -64.5 -66.0 -67.5 -69.0 -70.5 -72.0 ...
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... Zarlink Semiconductor Inc. Data Sheet ADDRESS = 1Eh WRITE/READ VERIFY Power Reset Value - DRESET 0000 0000 1 0 ADDRESS 1Fh is RESERVED ADDRESS = 20h WRITE/READ VERIFY Power Reset Value B0 XX11 0000 0 ADDRESS = 21h WRITE/READ VERIFY Power Reset Value ...
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... 1992.2 Hz 7.8 Hz 7.8 Hz ± -2.1 dB 0.2 dB 4000 Hz 31.4 Hz non-linear ADDRESS = 24h WRITE/READ VERIFY 1992.2 Hz 7 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 Power Reset Value 0000 0000 ADDRESS 25h is RESERVED ...
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... A 2-wire digital phone for PABX, key-systems and other proprietary applications is implemented with the MT8971/72/MT9094 combination. Figures 9 and 10 show the 4-wire and 2-wire applications, respectively. MT9094 ADDRESS = 26h WRITE/READ VERIFY 500 Hz 2.0 Hz non-linear 22 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 ...
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... 0.1µF VBias MT9094 LCD 23 Zarlink Semiconductor Inc. Data Sheet 330Ω + 511Ω 0.1µF 100K + T VBias Electret Microphone 100K 0.1µF 511Ω 40Ω nom. 32Ω min. 75Ω 150Ω 75Ω ...
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... Electret + Microphone R 0.1µF VBias MT9094 LCD 24 Zarlink Semiconductor Inc. Data Sheet 330Ω + VBias +5V + – 1µF + Electret Microphone + 40Ω nom. 32Ω min. 75Ω 150Ω 75Ω +5V .1µF 1000pF 1000pF 1000pF caps ...
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... F0i MT8930 DPhone-∏ SNIC DSTo DSTi with HDLC DSTi DSTo Controller AD0-7 IRQ IRQ CS SCLK (ALE) (RD) (WR) AS (ALE) AD0-7 8051 INTEL IRQ 25 Zarlink Semiconductor Inc. Data Sheet HSPKR+ HSPKR- Handset M+ MT9094 M- MIC+ Microphone MIC- SPKR+ Speaker SPKR- DATA1 E R/W (RD) (WR) MCS- 51 ...
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... Lout to Central PBX Figure 10 - Voice/Data Digital Telephone Set Circuit MT9094 C4 C4i F0 F0i MT8972 MT9094 DPhone-∏ DNIC DSTi DSTo DSTi DSTo 10.24 MHz SCLK INTEL MCS-51 26 Zarlink Semiconductor Inc. Data Sheet HSPKR+ HSPKR- Handset M+ M- MIC+ Microphone MIC- SPKR+ Speaker SPKR- CS DATA1 ...
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... Address 15h bits (as required) 1Eh 00h 1Dh 70h (or as required) 20h 30h (or as required) 23h as required 24h as required 26h as required 1Eh 61h 0Eh 82h 1Eh 61 (on) 69 (off) 61 (on) 69 (off) etc... 27 Zarlink Semiconductor Inc. Data Sheet DATA DATA DATA ...
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... NCTG2-1 (as required) 0Eh 02h 9Bh (assuming a concurrent handset call) 01h (assuming all other bits are µ-Law 0Fh 1Eh 71h (on) 31h (off) 71h (on) etc... 28 Zarlink Semiconductor Inc. Data Sheet ...
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... A f 4092 4096 4100 CLK Sym. Min. Typ. Max. I DDC1 I 1.5 DDF1 I 1.5 DDF3 I 1.5 DDF4 I 1.5 DDF5 I 1.0 DDF6 I 7.0 14 DDFT 29 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 ±20 mA °C -65 +150 750 mW ±2.0 KV ±100 mA Units Test Conditions V V Noise margin = 400 mV V Noise margin = 400 mV ° ...
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... Voltages are with respect to ground (V Sym. Min. Typ. Max. V 4.8 --- --- OH V --- --- 0.2 OL --- --- 1200 --- --- 7200 62 62 Zarlink Semiconductor Inc. Data Sheet ) unless otherwise stated. SS Units Test Conditions V V Max. Load = 100 µA V µ 2.4V DSTo, WD, OH DATA1, DATA2 0.4V DSTo, WD, ...
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... D 360 AX D 750 DX 380 130 750 PSSR 37 PSSR1 40 PSSR2 35 PSSR3 40 31 Zarlink Semiconductor Inc. Data Sheet for A-Law, at the CODEC rms Ref Units Test Conditions µ-Law Vp-p Vp-p A-Law Both at CODEC dB MICA/u=0* dB MICA/u=1* MIC± or M± to PCM 1020Hz dB MICA/u=0* dB MICA/u=1* from nominal MIC± ...
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... Typ. Max. G -17.2- -16.7 16.2 AS1 G 13.1 -12.6 -12.1 AS2 G -0.3 +0 -0.3 +0 Zarlink Semiconductor Inc. Data Sheet for A-Law, at the CODEC. (V rms Units Test Conditions µ-Law Vp-p Vp-p A-Law dB PCM to SPKR± dB PCM to HSPKR±, RxA/u=0* dB PCM to HSPKR±, RxA/u=1* 1020Hz dB PCM to SPKR± dB PCM to HSPKR±, RxA/u=0* dB PCM to HSPKR± ...
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... S 0.5 D ‡ Sym. Min. Typ. Max. V 2. Zarlink Semiconductor Inc. Data Sheet Test Conditions NCTG0=0, NCTG1=0 NCTG0=1, NCTG1=0 NCTG0=0, NCTG1=1 NCTG0=1, NCTG1=1 load > 34 ohms across SPKR± Units Test Conditions ohms across HSPKR± pF each pin: HSPKR+ HSPKR- ...
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... F0iW t 100 125 DSToD t 30 DSTiS t 50 DSTiH 1 bit cell t C4P t DSToD t DSTiS t t F0iH T t F0iW Figure 11 - ST-BUS Timing Diagram 34 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions = C4H C4L t DSTiH ...
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... TRANSMIT MT9094 ‡ Sym. Min. Typ 333 Figure 12 - Serial Microport Timing Diagram 35 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...