zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet
zl50019gag2
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zl50019gag2 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Enhanced 2 K Digital Switch with ZL50019GAC ZL50019QCC ZL50019QCG1 ZL50019GAG2 **Pb Free Tin/Silver/Copper • Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and output data rates can differ • ...
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... PBX and IP-PBX • Small and medium digital switching platforms • Remote access servers and concentrators • Wireless base stations and controllers • Multi service access platforms • Digital Loop Carriers • Computer Telephony Integration ZL50019 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Users can employ the microprocessor port to perform register read/write, connection memory read/write and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port. ZL50019 3 Zarlink Semiconductor Inc. Data Sheet 15 -1 pattern. On the ...
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... Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.3 Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.4 Pull-In/Hold-In Range (also called Locking Range 14.0 Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.1 Input Clock Cycle to Cycle Timing Variation Tolerance 14.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ZL50019 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 24.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 24.1 Memory Address Mappings 24.2 Connection Memory Low (CM_L) Bit Assignment 24.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 25.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 27.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ZL50019 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 44 - FPo2 and CKo2 or FPo3 and CKo3 (16.384 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 46 - FPo4 and CKo4 Timing Diagram (1.544/2.048 MHz 112 Figure 47 - CKo5 Timing Diagram (19.44 MHz 112 Figure 48 - REF0 - 3 Reference Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ZL50019 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 49 - Output Timing (ST-BUS Format 116 ZL50019 List of Figures 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 44 - Output Jitter Control Register (OJCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 45 - Stream Input Control Register (SICR0 - 31) Bits Table 46 - Stream Input Quadrant Frame Register (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 47 - Stream Output Control Register (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 48 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ZL50019 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 52 - Address Map for Memory Locations (A13 = Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 54 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 55 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ZL50019 List of Tables 9 Zarlink Semiconductor Inc. Data Sheet ...
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... DPLL’s automatic reference switching with and without preference operations in Automatic Timing Mode. • Clarified threshold calculations. • Added description to clarify that only two consecutive references can be used in automatic timing mode with a preferred reference. 10 Zarlink Semiconductor Inc. Data Sheet Change Change ...
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... CORE D11 D13 STOHZ1 D3 D8 D14 IRQ D12 D15 Zarlink Semiconductor Inc. Data Sheet STio23 STio21 STio20 NC NC IC_ IC_ CKi OSCi ODE OPEN OPEN IC_ OSCo IC_GND V STio15 SS OPEN FPo_ OSC_ ...
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... Zarlink Semiconductor Inc. Data Sheet 148 146 144 142 140 138 136 134 132 130 STio_19 128 STio_18 STio_17 126 STio_16 124 STOHZ_15 VSS 122 STOHZ_14 ...
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... ZL50019 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3 Ground SS 13 Zarlink Semiconductor Inc. Data Sheet Description ...
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... This pin is held in high impedance state when JTAG is not enabled. Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected. Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low. No Connect These pins MUST be left unconnected. 14 Zarlink Semiconductor Inc. Data Sheet ...
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... If REF1 fails, REF_FAIL1 will be driven high. If REF2 fails, REF_FAIL2 will be driven high. If REF3 fails, REF_FAIL3 will be driven high. If the device is in slave mode, these pins are driven low, unless SLV_DPLLEN (bit 13) in the Control Register (CR) is set. 15 Zarlink Semiconductor Inc. Data Sheet or to DD_IO or DD_IO ...
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... See Section 6.0 on page 24 for details. In Divided Slave mode, the frequency of CKo0 - 3 cannot be higher than input clock (CKi). CKo4 and CKo5 are only available in Master mode or when the SLV_DPLLEN bit in the Control Register is set high while the device is in one of the slave modes. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps, a 16.384 MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR). 17 Zarlink Semiconductor Inc. Data Sheet Input (5 V-Tolerant ...
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... When an output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel. When the STio channel is active, the STOHZ drives low for the duration of the corresponding output channel. STOHZ outputs are available for STio0 - 157 only. 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Motorola interface. A read access is indicated when it goes low for the Intel interface. Address V-Tolerant Inputs) These pins form the 14-bit address bus to the internal memories and registers. 19 Zarlink Semiconductor Inc. Data Sheet ...
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... Refer to Section Section 17.2 on page 46 for details. 20 Zarlink Semiconductor Inc. Data Sheet Description ...
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... OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin, OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any ZL50019 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Input Clock Rate (CKi) 00 16.384 MHz 01 8.192 MHz 10 4.096 MHz 22 Zarlink Semiconductor Inc. Data Sheet Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse) Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) ...
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... FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR ZL50019 Channel Channel Zarlink Semiconductor Inc. Data Sheet ...
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... Table 3 on page 25. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode Selection (IMS) register. ZL50019 Channel Channel Zarlink Semiconductor Inc. Data Sheet Channel N = 127 Channel N = 255 ...
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... FPOFF2 register. In this instance, FPo_OFF2 can be labeled as FPo5. ZL50019 Output Timing Rate 244 4.096 122 8.192 61 16.384 244, 122 4.096, 8.192, 16.384 or 32.768 1.544 or 2.048 51 19.44 Table 3 - Output Timing Generation 25 Zarlink Semiconductor Inc. Data Sheet Output Timing Unit ns MHz ns MHz ns MHz ns MHz MHz ns MHz ...
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... Figure 7 - Output Timing for CKo0 and FPo0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz Figure 8 - Output Timing for CKo1 and FPo1 ZL50019 26 Zarlink Semiconductor Inc. Data Sheet ...
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... When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2 Figure 10 - Output Timing for CKo3 and FPo3 with CKoFPo3SEL1-0=”11” ZL50019 27 Zarlink Semiconductor Inc. Data Sheet ...
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... While there is no frame pulse output directly tied to the CKo4, the output clocks are based on the frame pulse generated by FPo0 FPo5 (FPo_OFF2) FP19EN = 1 CKO5EN = 1 CK5 = 19.44 MHz Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2) ZL50019 Figure 11 - Output Timing for CKo4 28 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 13 - Input Bit Delay Timing Diagram (ST-BUS) ZL50019 Channel 0 Channel Bit Delay = 1 Channel 0 Channel Zarlink Semiconductor Inc. Data Sheet Channel 2 Channel 2 ...
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... Figure 14 - Input Bit Sampling Point Programming ZL50019 Last Channel Sampling Point = 1/4 Bit Last Channel Last Channel Zarlink Semiconductor Inc. Data Sheet Sampling Point = 3/4 Bit Channel Channel Sampling Point = 1/2 Bit Channel Sampling Point = 4/4 Bit Channel ...
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... Channel Bit Advancement = 1 Channel Zarlink Semiconductor Inc. Data Sheet Nominal Channel n+1 Boundary 111 11 111 00 111 10 111 01 ...
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... Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) ZL50019 Last Channel Channel Fractional Bit Advancement = 1/4 Bit Last Channel Channel Fractional Bit Advancement = 1/2 Bit Last Channel Channel Fractional Bit Advancement = 3/4 Bit Channel Zarlink Semiconductor Inc. Data Sheet ...
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... If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. ZL50019 HiZ CH2 CH3 STOHZ Advancement (Programmable in 4 steps of 1/4 bit for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps Programmable in 2 steps of 1/2 bit for 16.384 Mbps) 33 Zarlink Semiconductor Inc. Data Sheet Last-2 Last-1 Last CH0 ...
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... CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 CH4 CH5 CH6 CH7 CH8 CH9 frames + ( Zarlink Semiconductor Inc. Data Sheet n n-m > 7 STio < STi STio >= STi n-m Frame L-2 L-1 CH0 CH1 CH2 CH3 ...
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... Frame L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 35 Zarlink Semiconductor Inc. Data Sheet Frame L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 L-2 L-1 CH0 CH1 CH2 CH3 ...
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... CKi ZL50019 Zarlink Semiconductor Inc. Data Sheet BPD2 BPD1 BPD0 0 0 ...
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... 8/ 8/ 8/16 M Table 7 - ZL50019 Operating Modes 37 Zarlink Semiconductor Inc. Data Sheet Output Clock Pins Data Pins Reference Lock Enabled Clock Source CKo0-3 CKo4-5 CKo0-3 CKo4-5 STi Freerun, Holdover Yes Yes CKi* or REF0-3 Cko2 CKi ...
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... In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the reference input clocks. The DPLL is internally either in normal or holdover mode. In the following two sections, the reference selection and state machine operation in automatic mode will be explained in more details. ZL50019 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Ref 0 and 1 failed and (Ref 2 or Ref 3 valid) All Ref failed All Ref failed All Ref failed All Ref failed Ref 2 and 3 failed and (Ref 0 or Ref 1 valid) 39 Zarlink Semiconductor Inc. Data Sheet Ref 1 Holdover 1 Ref 2 valid Holdover 2 Ref 2 Ref 2 failed ...
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... Option 2 Option 3 Option 4 Table 8 - Preferred Reference Selection Options Figure 22 shows the state diagram for the four valid options of automatic reference switching with a preferred reference. ZL50019 Ref 0 Ref 1 Ref 2 Ref 3 40 Zarlink Semiconductor Inc. Data Sheet Secondary Reference Ref 1 Ref 2 Ref 3 Ref 0 ...
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... Ref 2 valid Ref 0 and 3 failed Ref 3 valid Holdover 3 Ref 3 failed Ref 0 and 3 failed Ref 0 failed or Ref 3 valid Holdover 0 Ref 0 valid and Ref 3 failed Ref 3 valid 41 Zarlink Semiconductor Inc. Data Sheet Preferred Ref 0 Ref 1 Preferred Ref 1 Ref 2 Preferred Ref 2 Ref 3 Preferred Ref 3 ...
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... Table 29 on page 64, Table 37 on page 70 and Table 43 on page 77 for the detailed bit description of the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register (RCSR) and Reference Frequency Status Register (RFSR), respectively. ZL50019 8 kHz 1.544 MHz (DS1) 2.048 MHz (E1) 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz 42 Zarlink Semiconductor Inc. Data Sheet ...
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... For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is ±1023UI . p-p 14.3 Jitter Transfer Function The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz. ZL50019 43 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz clock period (10 ns). Single period deviation limits are more relaxed than multi period limits, and are used for early detection of the reference loss, or huge phase jumps. The values for the upper and lower limits are shown in the following table: ZL50019 44 Zarlink Semiconductor Inc. Data Sheet ...
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... UIp-p 0.2 UIp-p 0.2 UIp-p 0.2 UIp-p 0.2 UIp-p Stratum 4E Default Limits ( units) -82.487 ppm -64.713 ppm 0 ppm 64.713 ppm 82.487 ppm Table 12 - Multi-Period Hysteresis Limits 45 Zarlink Semiconductor Inc. Data Sheet Relaxed Stratum 4E Limits ( units) -250 ppm -240 ppm 240 ppm 250 ppm ...
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... MHz, the waiting time is 500 µs; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the waiting time is 2 ms. ZL50019 supply (normally +3 established before the DD_IO supply may be powered up at the same time DD_CORE supply by more than 0.3 V. DD_IO 46 Zarlink Semiconductor Inc. Data Sheet ...
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... ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 µs) between completion of connection memory programming and starting the BER receiver before the BER receiver can correctly identify BER errors bit BER counter is used to count the number of bit errors. ZL50019 15 -1 pseudorandom code (ITU O.151). 47 Zarlink Semiconductor Inc. Data Sheet ...
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... ITU-T G.711 A-law ITU-T G.711 µ-law 01 10 A-law without Alternate Bit Inversion (ABI) µ-law without Magnitude 11 Inversion (MI) 48 Zarlink Semiconductor Inc. Data Sheet Data Coding (V/D bit = 1) No code Alternate Bit Inversion (ABI) Inverted Alternate Bit Inversion (ABI) All bits inverted ...
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... Replaces LSB of every channel in Quadrant y with ‘0’ Replaces LSB of every channel in Quadrant y with ‘1’ Replaces MSB of every channel in Quadrant y with ‘0’ Replaces MSB of every channel in Quadrant y with ‘1’ 49 Zarlink Semiconductor Inc. Data Sheet Quadrant 3 Channel Channel ...
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... The Device Identification Register - The JTAG device ID for the ZL50019 is 0C36314B Version Part Number Manufacturer ID LSB 21.4 BSDL A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE-1149.1 test interface. ZL50019 <31:28> 0000 <27:12> 1100 0011 0110 0011 <11:1> ...
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... BERLR1 DPLLCR RFR CFRL CFRU FOR LDTR LDIR SRLR RCCR RCSR IR IMR ICR RSR RMR RFSR OJCR 51 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware Switch/Hardware Hardware Only DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware DPLL/Hardware ...
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... H 0360 - R Only BER Receiver Error Registers 037F H Table 16 - Address Map for Registers (A13 = 0) (continued) ZL50019 Register Abbreviation Name SICR0 - 31 SIQFR0 - 31 SOCR0 - 31 BRSR0 - 31 BRLR0 - 31 BRCR0 - 31 BRER0 - 31 52 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware ...
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... FPIN CKINP FPINP CKIN LP POS 1 Description CKIN1 - 0 FPi Active Period 122 ns 10 244 ns 11 Table 17 - Control Register (CR) Bits 53 Zarlink Semiconductor Inc. Data Sheet CKIN VAR MBPE OSB MS1 MS0 0 EN CKi 16.384 MHz 8.192 MHz 4.096 MHz ...
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... Active (Controlled by CM) Memory Selection 00 Connection Memory Low Read/Write 01 Connection Memory High Read/Write 10 Data Memory Read 11 Reserved 54 Zarlink Semiconductor Inc. Data Sheet VAR MBPE OSB MS1 MS0 0 EN STOHZ0 - 15 HiZ Driven High HiZ Driven High ...
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... STi16-31 tied low internally STio16-31 are bi-directional BDL STio0 - 15 Operation 0 normal operation: STi0-15 are inputs STio0-15 are outputs 1 bi-directional operation: STi0-15 tied low internally STio0-15 are bi-directional 55 Zarlink Semiconductor Inc. Data Sheet TBER BPD BPD BPD MBPS EN 2 ...
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... Table 19 - Software Reset Register (SRR) Bits ZL50019 STIO_ BDH BDL RBER PD_EN EN Description Description 56 Zarlink Semiconductor Inc. Data Sheet TBER BPD BPD BPD MBPS SRST SRST SW DPLL ...
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... When this bit is low, CKo0 and FPo0 are in high impedance state. Table 20 - Output Clock and Frame Pulse Control Register (OCFCR) Bits ZL50019 FPOF2 FPOF1 FPOF0 CKO5 Description 57 Zarlink Semiconductor Inc. Data Sheet CKO4 CKO CKO CKO CKO EN FPO3 FPO2 FPO1 FPO0 EN EN ...
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... CKO2 FPO2 FPO2 P POS P P POS Description CKOFPO3 FPo3 SEL1 - 0 00 244 ns 01 122 Zarlink Semiconductor Inc. Data Sheet CKO1 FPO1 FPO1 CKO0 FPO0 P P POS P P CKo3 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz ...
Page 59
... Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set. Table 21 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued) ZL50019 FPO3 FPO3 CKO2 FPO2 FPO2 P POS P P POS Description 59 Zarlink Semiconductor Inc. Data Sheet CKO1 FPO1 FPO1 CKO0 FPO0 P P POS FPO0 POS ...
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... Data Rate FPo_OFF[n] (Mbps) Pulse Cycle Width 2.048 one 4.096 MHz clock 4.096 one 8.192 MHz clock 8.192 one 16.384 MHz clock 16.384 one 16.384 MHz clock 60 Zarlink Semiconductor Inc. Data Sheet FOF[n] FOF[n] FOF[n] FOF[n] FOF[n] OFF2 OFF1 OFF0 ...
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... Description BER BER BER BER BER BER F10 Description 61 Zarlink Semiconductor Inc. Data Sheet OUT IN ERR ERR BER BER BER BER BER ...
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... F24 F23 F22 F21 Description BER BER BER BER BER BER L10 Description 62 Zarlink Semiconductor Inc. Data Sheet BER BER BER BER BER F20 F19 F18 F17 F16 BER BER BER BER ...
Page 63
... BER BER BER BER BER L26 L25 L24 L23 L22 Description ST4_ LIM Description 63 Zarlink Semiconductor Inc. Data Sheet BER BER BER BER BER L21 L20 L19 L18 L17 L16 ...
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... Zarlink Semiconductor Inc. Data Sheet R1F1 R1F0 R0F2 R0F1 R0F0 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved 8 kHz 1.544 MHz 2.048 MHz 4 ...
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... Zarlink Semiconductor Inc. Data Sheet R1F1 R1F0 R0F2 R0F1 R0F0 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz Reserved 8 kHz 1.544 MHz 2.048 MHz 4 ...
Page 66
... CFN CFN CFN CFN Description 66 Zarlink Semiconductor Inc. Data Sheet CFN CFN CFN CFN CFN CFN MCLK is frequency of DPLL master MCLK = = 43980465 29F16B1 H = 43979585 ...
Page 67
... Description LDT LDT LDT LDT LDT LDT Description LDT = MAX_EXP_JITTER (ns 15.2 (ns) 67 Zarlink Semiconductor Inc. Data Sheet FOF FOF FOF FOF FOF LDT LDT LDT ...
Page 68
... SRL SRL SRL SRL SRL SRL Description MTR PRS PRS 1 Description 68 Zarlink Semiconductor Inc. Data Sheet LDI LDI LDI LDI LDI LDI SRL SRL SRL SRL SRL ...
Page 69
... PMS2 PMS1 PMS0 Preference as per the setting 110 - 111 69 Zarlink Semiconductor Inc. Data Sheet PRS PMS PMS PMS FDM FDM REF0 REF1 REF2 REF3 Preference Mode No Preference of the PRS1 - 0 bits ...
Page 70
... DPLL TIMING Mode 0 0 Automatic 0 1 Normal 1 0 Holdover 1 1 Freerun SLM LST RFR2 RFR1 Description 70 Zarlink Semiconductor Inc. Data Sheet PMS PMS PMS FDM FDM RFR0 RES1 RES0 DPM1 DPM0 ...
Page 71
... REF REF 3 DPM1 DPM0 DPLL Timing Mode State 0 0 MTIE 0 1 Normal 1 0 Holdover 1 1 Freerun 71 Zarlink Semiconductor Inc. Data Sheet RFR0 RES1 RES0 DPM1 DPM0 Reference 8 kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 19.44MHz Reserved ...
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... Note 2: Any of these bits can be cleared by setting the appropriate bit in the Interrupt Clear Register. Table 38 - Interrupt Register (IR) Bits - Read Only ZL50019 Description 72 Zarlink Semiconductor Inc. Data Sheet LCI RCI HOI 0 0 ...
Page 73
... In normal functional mode, this bit MUST be set to one. Table 40 - Interrupt Clear Register (ICR) Bits ZL50019 Description Description 73 Zarlink Semiconductor Inc. Data Sheet LIM RIM HIM ICB ICB ICB ...
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... Table 11, “Values for Single Period Limits” on page 45) Table 41 - Reference Failure Status Register (RSR) Bits - Read Only ZL50019 FML FMU Description 74 Zarlink Semiconductor Inc. Data Sheet FML FMU ...
Page 75
... FMU FL FU FML FMU Description MML MMU Description 75 Zarlink Semiconductor Inc. Data Sheet FML FMU MML MMU ML MU ...
Page 76
... When this bit is high, it masks the single-period lower limit check (or forces pass) for REF0. Table 42 - Reference Mask Register (RMR) Bits (continued) ZL50019 MML MMU Description 76 Zarlink Semiconductor Inc. Data Sheet MML MMU ...
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... Description R3FS1 R3FS0 REF3 Frequency Measurement Zarlink Semiconductor Inc. Data Sheet MML MMU R1FS R1FS R1FS R0FS R0FS R0FS ...
Page 78
... REF0 Frequency Measurement Zarlink Semiconductor Inc. Data Sheet R1FS R1FS R0FS R0FS R0FS kHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz ...
Page 79
... STIN[n] STIN[n] STIN[n] BD2 BD1 BD0 SMP1 SMP0 Description Sampling Point (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 00 3/4 point 01 1/4 point 10 2/4 point 11 4/4 point 79 Zarlink Semiconductor Inc. Data Sheet OJP2 OJP1 OJP0 gives the best STIN[n] ...
Page 80
... STIN[n] STIN[n] STIN[n] STIN[n] BD2 BD1 BD0 SMP1 SMP0 Description STIN[n]DR3-0 0000 0001 0010 0011 0100 0101 - 1111 80 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] DR3 DR2 DR1 DR0 Data Rate Stream Unused 2.048 Mbps 4.096 Mbps 8 ...
Page 81
... LSB of each channel is replaced by “0” 101 LSB of each channel is replaced by “1” 110 MSB of each channel is replaced by “0” 111 MSB of each channel is replaced by “1” 81 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] ...
Page 82
... STIN[n]Q0C2-0 0xx 100 LSB of each channel is replaced by “0” 101 LSB of each channel is replaced by “1” 110 MSB of each channel is replaced by “0” 111 MSB of each channel is replaced by “1” 82 Zarlink Semiconductor Inc. Data Sheet STIN[n] STIN[n] STIN[n] STIN[n] ...
Page 83
... Mbps, 4.096 Mbps, 8.192 Mbps streams 1/4 bit 10 2/4 bit 11 3/4 bit STIN[n]DR3 - 0 0000 0001 0010 0011 0100 0101 - 1111 83 Zarlink Semiconductor Inc. Data Sheet STO[n] STO[n] STO[n] STO[n] STO[n] AD0 DR3 DR2 DR1 DR0 Additional Advancement (16.384 Mbps streams) ...
Page 84
... Table 49 - BER Receiver Length Register [n] (BRLR[n]) Bits ZL50019 ST[n] ST[n] ST[n] BRS7 BRS6 BRS5 Description ST[n] ST[n] ST[n] ST[n] BL8 BL7 BL6 BL5 Description 84 Zarlink Semiconductor Inc. Data Sheet ST[n] ST[n] ST[n] ST[n] ST[n] BRS4 BRS3 BRS2 BRS1 BRS0 ST[n] ST[n] ST[n] ST[n] ST[n] BL4 BL3 BL2 BL1 BL0 ...
Page 85
... Table 51 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only ZL50019 Description ST[n] ST[n] ST[n] ST[n] ST[n] ST[n] BC10 BC9 BC8 BC7 BC6 Description 85 Zarlink Semiconductor Inc. Data Sheet ST[n] ST[n] CBER SBER ST[n] ST[n] ST[n] ST[n] ST[n] BC5 BC4 BC3 BC2 BC1 BC0 0 ...
Page 86
... Stream Stream SSA SSA SCA SCA SCA Description 86 Zarlink Semiconductor Inc. Data Sheet Channel Address (Ch0 - 255 Channel [ ...
Page 87
... SCA Description MSG MSG MSG MSG MSG MSG Description 87 Zarlink Semiconductor Inc. Data Sheet SCA SCA SCA SCA SCA CMM MSG MSG PCC PCC ...
Page 88
... MSG MSG MSG MSG MSG Description PC PC Channel Output Mode Per Channel Tristate 0 1 Message Mode 1 0 BER Test Mode 1 1 Reserved 88 Zarlink Semiconductor Inc. Data Sheet MSG PCC PCC CMM ...
Page 89
... A-law w/o ABI µ-law w/o Magnitude 11 Inversion Output Coding Law OCL1-0 For Voice (V/D bit = 0) 00 CCITT.ITU A-law CCITT.ITU µ-law 01 10 A-law w/o ABI µ-law w/o Magnitude 11 Inversion 89 Zarlink Semiconductor Inc. Data Sheet V/D ICL ICL OCL OCL For Data (V/D bit = 1) ...
Page 90
... The crystal specification is as follows: Frequency Tolerance Oscillation Mode Resonance Mode Load Capacitance Maximum Series Resistance Approximate Drive Level ZL50019 OSCi 20 MHz 1 MΩ OSCo Figure 23 - Crystal Oscillator Circuit 20 MHz As required Fundamental Parallel Ω Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... For applications requiring ±32 ppm clock accuracy, the following requirements should be met: Frequency Tolerance Rise and Fall Time Duty Cycle ZL50019 +3.3 V OSCi +3 MHz OUT GND OSCo No Connection Figure 24 - Clock Oscillator Circuit 20.000 MHz ±32 ppm 10 ns 40% to 60% 91 Zarlink Semiconductor Inc. Data Sheet 0.1 uF ...
Page 92
... Sym. Min. Typ. Max. I 165 DD_CORE I DD_IO Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.5 5.0 V -0.5 2 -0.5 7 1.5 W ° +125 . ‡ Typ. Max. Units °C 25 +85 3.3 3.6 V 1.8 1.89 V 3.3 ...
Page 93
... Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 25 - Timing Parameter Measurement Voltage Levels ZL50019 Sym. Level V 0 DD_IO V 0 DD_IO V 0 DD_IO Timing Reference Points 93 Zarlink Semiconductor Inc. Data Sheet Units Conditions ...
Page 94
... AKH t 8 AKZ , with timing corrected to cancel time taken CSS t RWS t AS VALID ADDRESS VALID READ DATA AKD 94 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
Page 95
... AKH t 8 AKZ , with timing corrected to cancel time taken CSS t RWS t AS VALID ADDRESS t DS VALID WRITE DATA t AKD 95 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
Page 96
... AKH t 8 AKZ , with timing corrected to cancel time taken CSD VALID ADDRESS VALID READ DATA AKD 96 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
Page 97
... AKH t 8 AKZ , with timing corrected to cancel time taken CSD VALID ADDRESS t DS VALID WRITE DATA t AKD 97 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions pF (Note 1) ...
Page 98
... TCKP t TMSH t TDIH t TDOD Figure 30 - JTAG Test Port Timing Diagram Sym. Min. Typ. Max. -32 32 -100 100 IR Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Notes TRSTW ‡ Units Notes ...
Page 99
... FPIW t 110 FPIS t 110 FPIH t 220 CKIP t 110 CKIH t 110 CKIL t CKi, t CKi CVC 99 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes 61 115 ‡ Typ. Max. Units Notes 122 220 ...
Page 100
... Figure 31 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t FPIS CKi Input Frame Boundary Figure 32 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50019 t FPIW t FPIH t CKIP t CKIH t rCKI t FPIW t FPIH t CKIP t CKIH t rCKI 100 Zarlink Semiconductor Inc. Data Sheet t CKIL t fCKI t CKIL t fCKI ...
Page 101
... Ch0 t SIS4 t SIH4 Bit7 Bit6 Ch0 Ch0 t SIS8 t SIH8 Bit7 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 Ch0 101 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Bit6 V CT Ch0 Bit5 Bit4 V CT Ch0 Ch0 V Bit2 ...
Page 102
... SIH2 Bit0 Ch0 t SIS4 t SIH4 Bit0 Bit1 Ch0 Ch0 t SIS8 t SIH8 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 102 Zarlink Semiconductor Inc. Data Sheet V Bit2 Bit1 Bit0 Ch0 Ch0 Ch0 Bit1 V CT Ch0 Bit2 Bit3 V CT Ch0 Ch0 V Bit5 ...
Page 103
... Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 36 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps ZL50019 SIS16 t SIH16 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 103 Zarlink Semiconductor Inc. Data Sheet V Bit5 Bit6 Bit7 Ch0 Ch0 Ch0 ...
Page 104
... Ch0 t SOD16 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 104 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Master Mode Multiplied Slave Mode Divided Slave Mode ns ...
Page 105
... Ch0 Ch0 Ch0 Ch0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch0 Ch1 105 Zarlink Semiconductor Inc. Data Sheet Bit1 V CT Ch0 Bit2 Bit3 V CT Ch0 Ch0 Bit5 Bit6 Bit7 V Ch0 Ch0 Ch0 CT Bit1 ...
Page 106
... Valid Data Tristate t ZD Tristate Valid Data t DZ_ODE Valid Data HiZ Figure 40 - Output Drive Enable (ODE) 106 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 8 ns Master Mode 7 ns Multiplied Slave Mode 0 ns Divided Slave Mode 8 ns Master Mode ...
Page 107
... Input Frame Boundary FPo0 CKo0 (4.096 MHz) Figure 41 - Input and Output Frame Boundary Offset ZL50019 Sym. Min. Typ. Max FBOS FBOS t FBOS Output Frame Boundary 107 Zarlink Semiconductor Inc. Data Sheet Units Notes ns ns Input reference jitter is equal to zero. ...
Page 108
... Sym. Min. t 218 FPW0 t 117 FODF0 t 97 FODR0 t 218 CKP0 t 117 CKH0 t 97 CKL0 rCK0 fCK0 108 Zarlink Semiconductor Inc. Data Sheet rCK0 ‡ Typ. Max. Units Notes 244 249 127 ns L 127 ns 244 249 ns ...
Page 109
... Sym. Min. t 106 FPW1 t 56 FODF1 t 46 FODR1 t 106 CKP1 t 46 CKH1 t 46 CKL1 rCK1 fCK1 109 Zarlink Semiconductor Inc. Data Sheet rCK1 ‡ Typ. Max. Units Notes 122 127 122 127 ns C ...
Page 110
... Sym. Min FPW2 t 25 FODF2 t 25 FODR2 t 47 CKP2 t 17 CKH2 t 17 CKL2 rCK2 fCK2 110 Zarlink Semiconductor Inc. Data Sheet rCK2 ‡ Typ. Max. Units Notes ...
Page 111
... Sym. Min FPW3 t 12 FODF3 t 12 FODR3 t 17 CKP3 t 5 CKH3 t 12 CKL3 rCK3 fCK3 111 Zarlink Semiconductor Inc. Data Sheet rCK3 ‡ Typ. Max. Units Notes 30 30 ...
Page 112
... CKP4 t 241 CKH4 t 241 CKL4 rCK4 fCK4 t FPW5 t t FODF5 FODR5 t CKP5 t t CKH5 CKL5 t fCK5 112 Zarlink Semiconductor Inc. Data Sheet rCK4 ‡ Typ. Max. Units Notes 648 650 324 327 ns L 324 327 ‡ ...
Page 113
... Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 ‡ Sym. Min. Typ FPW5 FODF5 FODR5 CKP5 CKH5 CKL5 rCK5 fCK5 113 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes ...
Page 114
... See “Performance Characteristics Notes” on page 118. REF0-3 FPo[n] CKo[n] Figure 48 - REF0 - 3 Reference Input/Output Timing ZL50019 Sym. Min RPMIN -10 t RPMIN 114 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes‡ ns 1,2,3, ...
Page 115
... C5D Sym. Min C1D t -1 C2D t -2 C3D Sym. Min C1D t -1 C2D t -1 C3D 115 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes‡ 1-5, Max. Units Notes‡ 1-5, Max ...
Page 116
... CKo0 (4.096 MHz) CKo4 (1.544 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo5 (19.44 MHz) CKo3 (32.768 MHz) Figure 49 - Output Timing (ST-BUS Format) ZL50019 t C4D t C1D t C2D t C5D t C3D 116 Zarlink Semiconductor Inc. Data Sheet ...
Page 117
... Output Jitter Generation (Unfiltered except for CKo5) ‡ Typ. 810 800 710 670 1060 630 770 540 460 510 117 Zarlink Semiconductor Inc. Data Sheet Conditions/ Max. Units Notes‡ 0 ppm 1,5,7 0.03 ppm 1,4,8 260 ppm 1,3,7,9 82.5 ppm 1,3,7,9,12 64.5 ppm 248 ...
Page 118
... Multi-period near limits and far limits are programmed to +/-240 ppm & +/-250 ppm respectively. (ST4_LIM = 0) 14 load on output pin. ZL50019 at 3.3 V and are for design aid only: not guaranteed and not subject to production DD_IO . ppm . ppm µ s. 118 Zarlink Semiconductor Inc. Data Sheet ...
Page 119
... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
Page 120
... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
Page 121
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...