zl50017 Zarlink Semiconductor, zl50017 Datasheet
zl50017
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zl50017 Summary of contents
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... DD_IO S/P Converter STi[15:0] FPi CKi Input Timing MODE_4M0 MODE_4M1 Figure 1 - ZL50017 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Ordering Information ZL50017GAC ZL50017QCC ZL50017QCG1 ZL50017GAG2 **Pb Free Tin/Silver/Copper • ...
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... Description The ZL50017 is a maximum 1024 x 1024 channel non-blocking digital Time Division Multiplex (TDM) switch. It has sixteen input streams (STi0 - 15) and sixteen output streams (STio0 - 15). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. All of the input and output streams operate at the same data rate and can be programmed at any of the following data rates: 2 ...
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... Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 Test Access Port (TAP 11.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.3 Test Data Registers 11.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14.1 Memory Address Mappings 14.2 Connection Memory Low (CM_L) Bit Assignment 15.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ZL50017 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50017 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50017 256-Ball PBGA (as viewed through top of package Figure 3 - ZL50017 256-Lead LQFP (top view Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the Figure 6 - Input Timing when CKIN1 - 0 = “ ...
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... Table 10 - Stream Output Control Register (SOCR0 - 15) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 11 - Address Map for Memory Locations (A13 = Table 12 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = ZL50017 List of Tables 5 Zarlink Semiconductor Inc. ...
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... The following table captures the changes from January 2006 to November 2006. Page Item 1 The following table captures the changes from the October 2004 issue. Page Item 13 Pin Description “STio 0 - 15” on page 13 ZL50017 Updated Ordering Information. • Clarified STio 0-15 pin description. 6 Zarlink Semiconductor Inc. Data Sheet Change Change ...
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... NC NC STio2 Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package. Figure 2 - ZL50017 256-Ball PBGA (as viewed through top of package) ZL50017 DD_ STi0 NC NC FPi COREA ...
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... NC NC 248 VDD_IO NC 250 VSS NC 252 NC NC 254 NC NC 256 Figure 3 - ZL50017 256-Lead LQFP (top view) ZL50017 176 174 172 170 168 166 164 162 160 158 156 154 152 150 ...
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... M5, M12, 209, 214, P3, P14, T1, 216, 218, T16 222, 223, 228, 230, 232, 235, 242, 251 ZL50017 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3 Ground SS 9 Zarlink Semiconductor Inc ...
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... G3, D12, 144, 107, IC_GND C13, B14 148, 208 ZL50017 Description Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. ...
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... K1, L1, A7, 14, 55, A5, A6, A4, 56, 58, A3, A2, C1, 59, 243, B1, E9, D8, 244, 245, B8, D7 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197, 161, 164, 166, 168 ZL50017 Description No Connect These pins MUST be left unconnected. 11 Zarlink Semiconductor Inc. Data Sheet ...
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... C5, C4, E3, 183, 184, C2, B2, D2, 185, 187, F3, F4, E2, 198, 200, F2 201, 202, 203, 204, 205, 206 ZL50017 Description 4 M Input Clock Mode V-Tolerant Input with internal pull-down) These two pins should be tied together. MODE MODE _4M1 _4M0 0 0 CKi = 8.192 MHz or 16.384 MHz ...
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... N11 39 R/W_WR R12 42 DS_RD ZL50017 Description Serial Output Streams V-Tolerant Slew-Rate-Limited Three-state I/Os with Enabled Internal Pull-downs) The data rate of all the output streams are programmed through the “Data Rate Selection Register” on page 31. In the 2.048 Mbps mode, these pins output serial TDM data streams at 2.048 Mbps with 32 channels per frame ...
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... Data Rates and Timing The ZL50017 has 16 serial data inputs and 16 serial data outputs. All streams are programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame. ...
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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The frequency of the input clock (CKi) for the ZL50017 must be at least twice the input/output data rate. For example, if the input/output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz. Following the example above, if the input/output data rate is 4 ...
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... Channel 0 STi (8.192 Mbps) Channel 0 STi (16.384 Mbps) Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR ZL50017 Channel Channel N = 127 5 4 Channel N = 255 Zarlink Semiconductor Inc. ...
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... ST-BUS and GCI-Bus Timing The ZL50017 is capable of operating using either the ST-BUS or GCI-Bus standards. By default, the ZL50017 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. ...
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... Bit Delay = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 7 - Input Bit Delay Timing Diagram (ST-BUS) ZL50017 Channel 0 Channel ...
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... Input Bit Sampling Point Programming In addition to the input bit delay feature, the ZL50017 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control Register (SICR0 - 15). For input streams the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position ...
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... By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n] (bits the Stream Output Control Register (SOCR0 - 15) as described in Table 10 on page 33. The output bit advancement can vary from bits. ZL50017 Nominal Channel n+1 Boundary 6 5 ...
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... STo[n]FA1 ( Mbps) Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 11 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) ZL50017 Channel 0 Channel ...
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... STio9 L-2 L-1 CH0 CH1 CH2 CH3 CH3 L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. Figure 12 - Data Throughput Delay for Variable Delay ZL50017 n-m < < n-m < frame - (m-n) 1 frame + (n-m) Table 1 - Delay for Variable Delay Mode ...
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... When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50017 will operate in one of the special modes described in Table 13 on page 36. When the per-channel message mode is enabled, MSG7 - 0 (bit the Connection Memory Low (CM_L) will be output via the serial data stream as message output data ...
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... D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a CM_H read operation will be used and D15 - 5 will output zeros. Refer to Figure 15 on page 39, Figure 16 on page 40, Figure 17 on page 41 and Figure 18 on page 42 for the microprocessor timing. ZL50017 ...
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... Test Access Port (TAP) Controller. 11.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50017 test functions. It consists of three input pins and one output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50017 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning ...
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... Internal Flag Register H 0100 - R/W Stream Input Control Registers 010F H 0200 - R/W Stream Output Control Registers 020F H Table 3 - Address Map for Registers (A13 = 0) ZL50017 Register Abbreviation Name CR IMS SRR DRSR IFR SICR0 - 15 SOCR0 - 15 27 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware Switch/Hardware ...
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... When this bit is high, the variable delay mode is enabled on a device-wide basis. 3 MBPE Memory Block Programming Enable When this bit is high, the connection memory block programming mode is enabled to program the connection memory. When it is low, the memory block programming mode is disabled. ZL50017 ...
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... Note: Unused output streams are tristated (STio = HiZ). Refer to SOCR0 - 15 (bit MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data mem- ory for access by CPU: MS1 - 0 Table 4 - Control Register (CR) Bits (continued) ZL50017 FPIN ...
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... Whenever the microprocessor writes a one to the MBPS bit, the block programming function is started. As long as this bit is high, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. Table 5 - Internal Mode Selection Register (IMS) Bits ZL50017 ...
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... Unused Reserved In normal functional mode, these bits MUST be set to zero DR3 - 0 Input/Output Data Rate Selection Bits: These bits set the data rate for both input and output streams 0101 - 1111 Table 7 - Data Rate Selection Register ZL50017 ...
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... FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits STIN[n]SMP1 - Unused Reserved In normal functional mode, these bits MUST be set to zero Table 9 - Stream Input Control Register (SICR0 - 15) Bits ZL50017 ...
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... STO[n]EN Output Stream Enable Bit When this bit is high the output stream is enabled. When this bit is low the output stream is set to high impedance 15 Note: [n] denotes output stream from 0 - Table 10 - Stream Output Control Register (SOCR0 - 15) Bits ZL50017 STIN[n] STIN[n] ...
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... Channels are used when serial stream is at 4.096 Mbps. 4. Channels 0 to 127 are used when serial stream is at 8.192 Mbps. 5. Channels 0 to 255 are used when serial stream is at 16.384 Mbps. Table 11 - Address Map for Memory Locations (A13 = 1) ZL50017 A8 Stream [n] A7 ...
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... The binary value of these 8 bits represents the input channel number. 0 CMM = 0 Connection Memory Mode = 0 If this is low, the connection memory is in the normal switching mode. Bit are the source stream number and channel number. Table 12 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 ZL50017 SSA ...
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... These two bits control the corresponding entry’s value on the STio stream. 0 CMM = 1 Connection Memory Mode = 1 If this is high, the connection memory is in the per-channel control mode which is per-channel tristate or per-channel message mode. Table 13 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 ZL50017 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50017 Symbol V DD_IO ...
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... Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 14 - Timing Parameter Measurement Voltage Levels ZL50017 Sym. Level V 0 DD_IO V 0 DD_IO V 0 ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 15 - Motorola Non-Multiplexed Bus Timing - Read Access ZL50017 ‡ Sym. Min. Typ. Max CSD t 15 DSD t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 16 - Motorola Non-Multiplexed Bus Timing - Write Access ZL50017 ‡ Sym. Min. Typ. Max CSD t 15 DSD t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing A0-A13 D0-D15 RDY Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access ZL50017 ‡ Sym. Min. Typ. Max CSD ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing A0-A13 D0-D15 RDY Figure 18 - Intel Non-Multiplexed Bus Timing - Write Access ZL50017 ‡ Sym. Min. Typ. Max CSD ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. TCK t TMSS TMS t TDIS TDi TDo TRST ZL50017 Sym. Min. t 100 TCKP t 20 TCKH t 20 TCKL ...
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... CKi Input Clock Cycle to Cycle Variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50017 Sym. Min. t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. FPi t CKi Input Frame Boundary Figure 20 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t CKi Input Frame Boundary Figure 21 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50017 Sym. t FPIW t FPIS t FPIH t CKIP t CKIH ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. Note 1: High impedance is measured by pulling to the appropriate rail with R discharge ZL50017 ‡ Sym. Min. Typ. Max. Units ...
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... Bit6 Bit7 Ch127 8.192 Mbps Ch127 STio0 - 15 Bit5 Bit6 Bit7 Bit0 16.384 Mbps Ch255 Ch255 Ch255 Ch0 Figure 22 - ST-BUS Input and Output Timing Diagram when Operated and 16 Mbps ZL50017 t SIS2 t SIH2 Bit7 Ch0 t SIS4 t SIH4 Bit7 Bit6 Ch0 Ch0 t ...
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... Bit6 Bit7 8.192 Mbps Ch127 Ch127 STio0 - 15 Bit5 Bit6 Bit7 Bit0 16.384 Mbps Ch255 Ch255 Ch255 Ch0 Figure 23 - GCI-Bus Input and Output Timing Diagram when Operated and 16 Mbps ZL50017 t SIS2 t SIH2 Bit0 Ch0 t SIS4 t SIH4 Bit0 Bit1 Ch0 Ch0 t ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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