zl50020 Zarlink Semiconductor, zl50020 Datasheet
zl50020
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zl50020 Summary of contents
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... DD_IO S/P Converter STi[31:0] FPi CKi Input Timing MODE_4M0 MODE_4M1 Figure 1 - ZL50020 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Enhanced 2 K Digital Switch ZL50020GAC ZL50020QCC ZL50020QCG1 ZL50020GAG2 **Pb Free Tin/Silver/Copper • ...
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... Computer Telephony Integration Description The ZL50020 is a maximum 2048 x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2 ...
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... Test Access Port (TAP 17.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.3 Test Data Registers 17.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 20.1 Memory Address Mappings 20.2 Connection Memory Low (CM_L) Bit Assignment 20.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 21.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ZL50020 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ZL50020 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50020 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50020 256-Ball PBGA (as viewed through top of package Figure 3 - ZL50020 256-Lead LQFP (top view Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the Figure 6 - Input Timing when CKIN1 - 0 = “ ...
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... Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6 - Connection Memory High After Block Programming Table 7 - ZL50020 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8 - Generated Output Frequencies Table 9 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 10 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11 - Quadrant Frame Bit Replacement ...
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... The following table captures the changes from the October 2004 issue. Page Item 13 Pin Description “CKi” on page 13 32 11.3, “Output Clock Frequencies“ ZL50020 Updated Ordering Information. • Clarified pin description for CKi. • Added new section to describe output clock frequencies. ...
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... STOHZ2 T V STio28 STio29 STio31 STio30 Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package. Figure 2 - ZL50020 256-Ball PBGA (as viewed through top of package) ZL50020 STi26 STi24 NC NC STio22 V DD_ STi0 CKo0 ...
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... VDD_IO STi_22 250 VSS STi_23 252 STio_24 STio_25 254 STio_26 STio_27 256 Figure 3 - ZL50020 256-Lead LQFP (top view) ZL50020 176 174 172 170 168 166 164 162 160 158 156 154 152 150 ...
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... M5, M12, 209, 214, P3, P14, T1, 216, 218, T16 222, 223, 228, 230, 232, 235, 242, 251 ZL50020 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3 Ground SS 10 Zarlink Semiconductor Inc ...
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... G3, D12, 144, 107, IC_GND B14, C13 148, 208 ZL50020 Description Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. ...
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... These two pins should be tied together and are typically used to select CKi = 4.096 MHz operation. See Table 7, “ZL50020 Operating Modes” on page 32 for a detailed explanation. See Table 13, “Control Register (CR) Bits” on page 39 for CKi and FPi selection using the CKIN1 - 0 bits. ...
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... C1, B1 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197 ZL50020 Description ST-BUS/GCI-Bus Frame Pulse Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. The frame pulse frequency is 8 kHz ...
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... R9, N10, P9, 27, 28, R10 30, 32, 34, 36, 37, 38 ZL50020 Description Serial Output Streams V-Tolerant Slew-Rate-Limited Three-state I/Os with Enabled Internal Pull-downs) The data rate of each output stream can be selected independently using the Stream Output Control Registers (SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM data streams at 2 ...
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... M13 41 MOT_INTEL G2 211 RESET ZL50020 Description Data Transfer Acknowledgment_Ready (5 V-Tolerant Three-state Output) This active low output indicates that a data bus transfer is complete for the Motorola interface. For the Intel interface, it indicates a transfer is completed when this pin goes from low to high. An external pull-up resistor MUST hold this pin at HIGH level for the Motorola mode ...
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... Data Rates and Timing The ZL50020 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame. ...
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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The frequency of the input clock (CKi) for the ZL50020 depends on the operation mode selected. In divided clock mode, CKi must be at least twice the highest input or output data rate. For example, if the highest input data rate is 4 ...
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... The ZL50020 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going clock format by programming CKINP (bit 8) in the Control Register (CR) ...
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... CKo while FPo goes high. The data rates define the number of channels that are available in a 125 µs frame pulse period. By default, the ZL50020 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse Selection Register (OCFSR) ...
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... Output Clock and Frame Pulse Selection Register (OCFSR). By default, the device delivers the negative output clock format. The ZL50020 can also deliver GCI-Bus format output frame pulses by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in GCI-Bus mode ...
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... Figure 8 - Output Timing for CKo1 and FPo1 CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 1 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 1 CKOFPO2EN = 1 CKO2P = 0 CKo2 = 16.384 MHz CKOFPO2EN = 1 CKO2P = 1 CKo2 = 16.384 MHz Figure 9 - Output Timing for CKo2 and FPo2 ZL50020 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Although input delay or output advancement features are available on streams which are operating in bi-directional mode it is not recommended can easily cause bus contention. If users require this function, special attention must be given to the timing to ensure contention is minimized. ZL50020 22 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Delay = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, and 8.192 and 16.384 Mbps modes respectively. Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) ZL50020 Channel 0 Channel ...
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... Input Bit Sampling Point Programming In addition to the input bit delay feature, theZL50020 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control Register (SICR0 - 31). For input streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position ...
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... The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point) Figure 13 - Input Bit Delay and Factional Sampling Point ZL50020 Nominal Channel n+1 Boundary 6 5 ...
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... Bit Adv = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS) ZL50020 Channel Bit Advancement = 1 ...
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... Last Channel STio[n] 1 STo[n]FA1 ( Mbps) Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) ZL50020 Last Channel Channel Fractional Bit Advancement = 1/4 Bit ...
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... Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. ZL50020 HiZ CH2 ...
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... The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode. ZL50020 n-m < < n-m < frame - (m-n) ...
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... UAEN (bit 15) in the Connection Memory Low. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50020 will operate in one of the special modes described in Table 33 on page 58. When the per-channel message mode is enabled, MSG7 - 0 (bit the Connection Memory Low (CM_L) will be output via the serial data stream as message output data. When the per-channel message mode is enabled, the µ ...
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... CKi rate (the output data rates are also limited as per Table 1). The input data rate cannot exceed the CKi rate in either Multiplied or Divided Clock modes, because input data are always sampled directly by CKi. ZL50020 11 10 ...
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... Table 7, “ZL50020 Operating Modes” on page 32 summarizes the different modes of operation available within the ZL50020. Each Major mode (explained below) has an associated Minor mode that is determined by setting the MODE_4M Input Control pins and the OPM bit in the Control Register (Table 13, “Control Register (CR) Bits” on page 39) indicated in the table ...
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... Refer to Figure 20 on page 63, Figure 21 on page 64, Figure 22 on page 65 and Figure 23 on page 66 for the microprocessor timing. 13.0 Device Reset and Initialization The RESET pin is used to reset the ZL50020. When this pin is low, the following functions are performed: • synchronously puts the microprocessor port in a reset state • ...
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... Pseudo Random Bit Generation and Error Detection The ZL50020 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 2 Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µ ...
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... The input channel and output channel encoding law are configured independently. If the output channel coding is set to be different from the input channel, the ZL50020 performs translation between the two standards. If the input and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection Memory High (CM_H) must be set on a per-channel basis not possible to translate between voice and data encoding laws ...
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... Test Access Port (TAP) Controller. 17.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50020 test functions. It consists of three input pins and one output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50020 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning ...
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... BER Receiver Length Registers 033F H 0340 - R/W BER Receiver Control Registers 035F H 0360 - R Only BER Receiver Error Registers 037F H Table 12 - Address Map for Registers (A13 = 0) ZL50020 Register Abbreviation Name CR IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERFR1 BERLR0 BERLR1 SICR0 - 31 SIQFR0 - 31 ...
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... Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 OPM Operation Mode. This bit is used to set the device in Master/Slave operation. Refer to Table 7, “ZL50020 Operating Modes” on page 32 for more details. 10 Unused Reserved. In normal functional mode, this bits MUST be set to zero. ...
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... Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 31 (bit2 - 0 MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data mem- ory for access by CPU: MS1 - 0 Table 13 - Control Register (CR) Bits (continued) ZL50020 FPIN CKINP ...
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... When this bit is low, all the BER receivers are disabled. To enable any BER receivers, this bit MUST be high. 4 TBEREN PRBS Transmitter Enable When this bit is low, all the BER transmitters are disabled. To enable any BER transmitters, this bit MUST be high. Table 14 - Internal Mode Selection Register (IMS) Bits ZL50020 STIO_ ...
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... Whenever the microprocessor writes a one to the MBPS bit, the block programming function is started. As long as this bit is high, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. Table 14 - Internal Mode Selection Register (IMS) Bits (continued) ZL50020 ...
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... Refer to Table 12, “Address Map for Registers (A13 = 0)” on page 32 for details regarding which registers are affected. 0 Unused Reserved In normal functional mode, these bits MUST be set to zero. Table 15 - Software Reset Register (SRR) Bits ZL50020 ...
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... CKo0 and FPo0 Enable When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled. EN When this bit is low, CKo0 and FPo0 are in high impedance state. Table 16 - Output Clock and Frame Pulse Control Register (OCFCR) Bits ZL50020 ...
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... FPO2POS Output Frame Pulse (FPo2) Position When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus). Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits ZL50020 FPO3 ...
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... When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus). Note: In Divided Clock modes, CKo3 - 1 cannot exceed frequency of CKi. Table 17 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued) ZL50020 ...
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... The binary value of these bits refers to the channel offset from original frame bound- ary. Permitted channel offset values depend on bits 1-0 of this register FOF[n] FPo_OFF[n] Control bits FOF[n]C 1 Note: [n] denotes output offset frame pulse from Table 18 - FPo_OFF[n] Register (FPo_OFF[n]) Bits ZL50020 FOF[n] FOF[n] FOF[n] FOF[n] FOF[n] OFF7 ...
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... BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero. Note: [n] denotes input stream from 0 - 15. Table 20 - BER Error Flag Register 0 (BERFR0) BIts - Read Only ZL50020 ...
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... BERL[n] BER Receiver Lock[n] If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked. Note: [n] denotes input stream from 0 - 15. Table 22 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only ZL50020 BER ...
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... The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits STIN[n]SMP1 - 0 STIN[n]SMP1-0 Table 24 - Stream Input Control Register (SICR0 - 31) Bits ZL50020 BER ...
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... Bit Name STIN[n]DR3 - 0 Input Data Rate Selection Bits: Note: [n] denotes input stream from 0 - 31. Table 24 - Stream Input Control Register (SICR0 - 31) Bits (continued) ZL50020 STIN[n] STIN[n] STIN[n] STIN[n] STIN[n] BD2 BD1 BD0 SMP1 SMP0 ...
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... These three bits are used to control STi[n]’s quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively. Table 25 - Stream Input Quadrant Frame Register (SIQFR0 - 31) Bits ZL50020 ...
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... These three bits are used to control STi[n]’s quadrant frame 0, which is defined as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively. Note: [n] denotes input stream from 0 - 31. Table 25 - Stream Input Quadrant Frame Register (SIQFR0 - 31) Bits (continued) ZL50020 ...
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... The binary value of these bits refers to the number of bits that the output stream advanced relative to FPo. The maximum value is 7. Zero means no advancement STO[n]DR3 - 0 Output Data Rate Selection Bits Note: [n] denotes output stream from 0 - 31. Table 26 - Stream Output Control Register (SOCR0 - 31) Bits ZL50020 STOHZ STO[n] ...
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... Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels these bits are set to zero, no BER test will be performed. Note: [n] denotes input stream from 0 - 31. Table 28 - BER Receiver Length Register [n] (BRLR[n]) Bits ZL50020 ...
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... The binary value of these bits refers to the bit error counts. When it reaches its maxi- mum value of 0xFFFF, the value will be held and will not rollover. Note: [n] denotes input stream from Table 30 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only ZL50020 ...
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... When this bit is low, normal switch without µ-law/A-law conversion. Connec- tion memory high will be ignored. When this bit is high, switch with µ-law/A-law conversion, and connection memory high controls the conversion method. Table 32 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 ZL50020 A8 Stream [ ...
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... In normal functional mode, these bits MUST be set to zero MSG7 - 0 Message Data Bits 8-bit data for the message mode. Not used in the per-channel tristate and BER test modes. Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 ZL50020 SSA ...
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... Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. Table 34 - Connection Memory High (CM_H) Bit Assignment ZL50020 MSG MSG MSG MSG MSG MSG ...
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... For proper µ Note 1: law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high. Note 2: Refer to G.711 standard for detail information of different laws. Table 34 - Connection Memory High (CM_H) Bit Assignment ZL50020 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V ZL50020 Symbol V DD_IO V ...
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... Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 19 - Timing Parameter Measurement Voltage Levels ZL50020 Sym. Level V 0 DD_IO V 0 DD_IO V 0 ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access ZL50020 ‡ Sym. Min. Typ. Max CSD t 15 DSD t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access ZL50020 ‡ Sym. Min. Typ. Max CSD t 15 DSD t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing A0-A13 D0-D15 RDY Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access ZL50020 ‡ Sym. Min. Typ. Max CSD ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing A0-A13 D0-D15 RDY Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access ZL50020 ‡ Sym. Min. Typ. Max CSD ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. TCK t TMSS TMS t TDIS TDi TDo TRST ZL50020 Sym. Min. t 100 TCKP t 20 TCKH t 20 TCKL ...
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... CKi Input Clock Cycle to Cycle Variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 Sym. Min. t ...
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... Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. FPi t CKi Input Frame Boundary Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t CKi Input Frame Boundary Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50020 Sym. t FPIW t FPIS t FPIH t CKIP t CKIH ...
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... Bit0 2.048 Mbps Ch31 STi0 - 31 Bit0 4.096 Mbps Ch63 STi0 - 31 Bit1 Bit0 Ch127 Ch127 8.192 Mbps Input Frame Boundary Figure 27 - ST-BUS Input Timing Diagram when Operated Mbps ZL50020 ‡ Sym. Min. Typ. Max SIS2 t 5 SIS4 t 5 SIS8 ...
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... Ch31 STi0 - 31 Bit7 4.096 Mbps Ch63 STi0 - 31 Bit6 Bit7 Bit0 Ch127 Ch127 Ch0 8.192 Mbps Input Frame Boundary Figure 29 - GCI-Bus Input Timing Diagram when Operated Mbps ZL50020 SIS16 t SIH16 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 t SIS2 t SIH2 ...
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... Mbps @16.384 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 t SIS16 t SIH16 ...
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... Ch0 t SOD16 STio0 - 31 Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 16.384 Mbps Output Frame Boundary Figure 32 - GCI-Bus Output Timing Diagram when Operated Mbps ZL50020 t SOD2 Bit7 Ch0 t SOD4 Bit7 Bit6 Ch0 Ch0 Bit6 Bit5 Bit4 Bit3 Ch0 ...
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... Note 1: High impedance is measured by pulling to the appropriate rail with R discharge FPo0 CKo0 STio STio Figure 33 - Serial Output and External Control ODE t ZD_ODE STio HiZ ZL50020 ‡ Sym. Min. Typ. Max ZD_ODE , with timing corrected to cancel the time taken to ...
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... FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary FPo0 CKo0 (4.096 MHz) Figure 35 - Input and Output Frame Boundary Offset ZL50020 ‡ Sym. Min. Typ. Max. t FBOS FBOS t FBOS Output Frame Boundary 75 Zarlink Semiconductor Inc ...
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... CKo0 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 t FPW03 t ...
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... CKo1 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 t FPW1 t ...
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... CKo2 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 t FPW23 t ...
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... CKo3 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc- tion testing. ZL50020 t FPW3 t ...
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... MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay † Characteristics are over recommended operating conditions unless otherwise stated. FPo0 CKo0 (4.096 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo3 (32.768 MHz) ZL50020 t FPD t C1D t C2D t C3D Figure 40 - Output Timing (ST-BUS Format) 80 Zarlink Semiconductor Inc ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...