zl50050 Zarlink Semiconductor, zl50050 Datasheet
zl50050
Related parts for zl50050
zl50050 Summary of contents
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... Timing Unit C8i PLL V DD_PLL Figure 1 - ZL50050 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion ( ...
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... V core supply voltage • 3.3 V I/O supply voltage • tolerant inputs, outputs and I/Os • Pin-to-pin compatible with Zarlink’s MT90871 device Note 1: For software compatibility between ZL50050 and MT90871, please refer to Section 2.6. Applications • Central Office Switches (Class 5) • Media Gateways • ...
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... Device Overview The ZL50050 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports have two independent modes of operation, either 16 input and 16 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination input and 8 output streams operated at 32.768 Mbps. ...
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... Local Connection Memory 9.2 Backplane Connection Memory 9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.1 Memory Block Programming Procedure 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 Test Access Port (TAP 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL50050 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Bit Rate Registers (LOBRR0 - LOBRR15 14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR15 14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR15 14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ZL50050 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50050 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50050 PBGA Connections (196 PBGA mm) Pin Diagram (as viewed through top of package Figure 3 - 8,192 x 8,192 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4 - 4,096 x 4,096 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5 - 6,144 by 2,048 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates ...
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... Table 44 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 45 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 46 - Local Input Bit Rate Register (LIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 47 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 48 - Local Output Bit Rate Register (LOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ZL50050 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 54 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 55 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ZL50050 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... BSTi4 BSTi5 BSTi7 K BSTi6 BSTi9 BSTi13 VDD_IO L BSTi8 BSTi11 BSTi14 M BSTi10 BSTi15 D15 N BSTi12 D13 D10 P GND D9 D8 Figure 2 - ZL50050 PBGA Connections (196 PBGA mm) Pin Diagram ZL50050 A12 A13 R A11 A14 ODE ...
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... N11 C16o M9 FP16o P12 ZL50050 Description Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the Backplane and Local sides (BSTi0-15 and LSTi0-15) must be aligned to this clock and the accompanying input frame pulse, FP8i ...
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... L1, K2, M1, L2, N1, K3, L3, M2 LSTi0-7 K14, J13, J14, K13, M14, J12, L14, M13 ZL50050 Description Backplane Serial Input Streams Tolerant Inputs with Internal Pull-downs). In Backplane Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16 ...
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... L12, K12 Backplane and Local Outputs and Control ODE B9 BORS G2 ZL50050 Description Local Serial Input Streams Tolerant Inputs with Internal Pull-downs). In Local Non-32 Mbps Mode, these pins accept serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8 ...
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... C5, B2, D2, C2 BSTo8-15 C3, F1, D3, E2, E1, E3, F2, F3 BCSTo0-1 A13, C10 ZL50050 Description Backplane Serial Output Streams Tolerant, Three-state Outputs with Slew-Rate Control). In Backplane Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16.384 Mbps (with 256 channels per stream), 8 ...
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... LSTo8-15 E12, F14, G14, G12, F12, F13, H14, G13 ZL50050 Description Local Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the LSTo0-15 outputs driven high, and the LCSTo0-1 outputs driven low. Following initialization, the ...
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... DS C8 R/W A9 DTA D9 ZL50050 Description Local Output Channel High-Impedance Control (5 V Tolerant Three-state Outputs). These pins control external buffering individually for a set of Local output streams on a per-channel basis. When LOW, the external output buffer will be tri-stated. When HIGH, the external output buffer will be enabled. ...
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... H12, J5, J10, K6, K7, K8 DD_PLL ZL50050 Description Device Reset (5 V Tolerant Input with Internal Pull-up). This input (active LOW) asynchronously applies reset and synchronously releases reset to the device. In the reset state, the outputs LSTo0-15 and BSTo0-15 are set to a HIGH or high impedance state, depending on the state of the LORS and BORS external control pins, respectively ...
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... G9, H6, H7, H8, H9, J6, J7, J8, J9, K5, K10, L4, L11, P1, P13, P14 Unused Pins IC_OPEN P9, P11 IC_GND C1, C11, C13, D1, M7, M8, N8, P8 ZL50050 Description Ground. Internal Connections - OPEN. These pins must be left unconnected. Internal Connections - GND. These pins must be tied LOW. 17 Zarlink Semiconductor Inc. Data Sheet ...
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... This gives the maximum 8,192 x 8,192 channel capacity. Often a system design needs to differentiate between a Backplane and a Local side needs to put the switch in a bi-directional configuration. In this case, the ZL50050 can be used as shown in Figure 4 to give 4,096 x 4,096 channel bi-directional capacity. BSTi0-15 ...
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... Mbps and 16.384 Mbps without loss to the switching capacity. 1.1 Flexible Configuration The ZL50050 can be configured non-blocking unidirectional digital switch non-blocking bi-directional digital switch blocking switch with various switching capacities. 1.1.1 ...
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... If the Backplane 32Mbps Mode is selected by setting the Control Register bit MODE32B HIGH, the settings in BIBRRn and BOBRRn are ignored. Similarly, if the Local 32Mbps Mode is selected by setting the Control Register bit MODE32L HIGH, the settings in LIBRRn and LOBRRn are ignored. ZL50050 20 Zarlink Semiconductor Inc. ...
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... Mbps. When the MODE32L bit in the Control Register is set high, the first 8 input streams, LSTi0-7, operate at 32.768 Mbps and the remaining 16 streams, LSTi8-15, will not be used and must be connected to a defined logic level. ZL50050 Rate Selection Capability (for each individual stream) 2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode. ...
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... Backplane Output Bit Rate Register (BOBRR0-15). The Backplane streams can also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 8 output streams, BSTo0-7, operate at 32.768 Mbps and the remaining 8 streams, BSTo8-15, will not be used and must be connected to a defined logic level. ZL50050 22 Zarlink Semiconductor Inc. Data Sheet ...
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... The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 6, ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50050 device will automatically detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame pulse ...
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... Mbps) GCI-Bus BSTi/LSTi0- Mbps) ST-BUS BSTi/LSTi0- Mbps) GCI-Bus BSTi/LSTi0- Mbps) ST-BUS BSTi/LSTi0- Mbps) GCI-Bus Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates ZL50050 Channel Channel ...
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... Input Frame Pulse and Generated Frame Pulse Alignment The ZL50050 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to the output of the device such that data which is input during Frame N is output during Frame N+2 ...
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... MHz frequency. Therefore, jitter tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the carrier frequency. In the case of the ZL50050, the input clock is 8.192 MHz, and the jitter associated with this clock can have the highest frequency component at 4.096 MHz. ...
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... Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a resolution of 1 bit. Refer to Figure 9 and Figure 10 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively. Refer to Figure 10 for Input Sampling Point Selection Timing at 8 Mbps data rates. ZL50050 ...
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... Ch254 BSTi/LSTi0-15 Bit Delay = 7 1 Ch254 BSTi/LSTi0-15 Bit Delay = 7 3/4 2 Please refer to Control Register (Section 14.1) for SMPL_MODE definition. Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps ZL50050 Ch0 Bit Delay, 1/4 Ch0 ...
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... MHz). For 2 Mbps, 4 Mbps, 8 Mbps or 16 Mbps streams, the advancement can cycles, -4 cycles or -6 cycles, which converts to approximately 0 ns, -15 ns shown in Figure 11. For 32 Mbps streams, the advancement can cycle, -2 cycles or -3 cycles, which converts to approximately 0ns, -7.6 ns, - -23 ns. ZL50050 Ch127 Ch0 0 ...
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... Register bit Table 2 - Local and Backplane Output Enable Control Priority ZL50050 Bit Advancement, 0 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Ch255 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 LE/BE OSB ...
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... Channel 0 will be transmitted during the C16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48. 4. With stream L/BSTo4 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1 will be transmitted during the C16o clock period numbers 9 and 17. ZL50050 LE/BE OSB ...
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... Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode) ZL50050 2 Channel No. 16 Mbps 8 Mbps 4 Mbps ...
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... Note 1: Clock period count is referenced to frame boundary. Note 2: The channel numbers presented relate to the data rate selected for a specific stream. Note 3: 3-1 to 3-4: See above for examples of channel control bits for streams of different data rates. ZL50050 Channel No. 16 Mbps 8 Mbps 11 Ch 255 ...
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... Bit 6 (8 Mbps) Chan 63 L/BSTo6 Bit 0 Chan 0 Bit 7 (4 Mbps) Chan 31 L/BSTo7 Bit 0 (2 Mbps) L/BCSTo0 L/BCSTo1 Figure 12 - Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps ZL50050 Chan 0 Chan 0 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 ...
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... For stream L/BSTo2, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock period number 2036 on L/BCSTo0. 4. For stream L/BSTo3, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock period number 12 on L/BCSTo1. ZL50050 35 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) ZL50050 2 Channel No. L/BCSTo1 32 Mbps 3 ...
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... Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) Note 1: Clock period count is referenced to frame boundary. Note 2: The channel numbers presented relate to the specific stream operating at a data rate of 32.768 Mbps. Note 3: 3-1 to 3-4: See above for examples of channel control bits. ZL50050 2 Channel No. L/BCSTo1 32 Mbps 1 Ch 511 ...
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... See “Local Connection Memory Bit Definition,” on page 49 and “Backplane Connection Memory Bit Definition,” on page 50 for programming details. When the LORS/BORS signal is asserted HIGH, the L/BCSTo0-1 outputs directly the values given in LE/BE. ZL50050 Channel 1 Channel 510 ...
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... Mbps 8 Mbps 16 Mbps 32 Mbps Table 5 - Variable Range for Input Streams Table 6 - Variable Range for Output Streams Input Channel Delay OFF frames + ( ZL50050 Input Channel Possible Input channel delay (α) Number ( 127 0 to 255 0 to 511 ...
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... Serial Input Data Frame N Data (No Delay) Serial Output Data Frame N-2 Data (No Delay) Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to ZL50050 α, is set to zero, the data throughput delay (T) is frames + (n - m). Frame N+1 Frame N+2 Frame N+3 Frame N+1Data ...
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... Frame N Serial Input Data Frame N-1 Data (α > 0) Serial Output Data Frame N-3 Data Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to ZL50050 Frame N+1 Frame N+2 Frame N+3 Input Channel Delay (from 1 to max # of channels) Frame N Data Frame N+1 Data Frame N+2 Data 3 Frames - α ...
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... The registers listed completely define the transmit and receive stream and channels. When BER transmission is enabled for these channels, the source bits and the Message Mode bits, LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The per-channel enable bits (LE ZL50050 ...
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... RESET pin; this delay is required for determination of the input frame pulse format. ZL50050 supply (nominally +3. established before the DD_IO supplies (nominally +1.8V). The V DD_PLL supply by more than 0 ...
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... Table 8. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated. ZL50050 RESET de-assertion Figure 21 - Hardware RESET De-assertion 44 Zarlink Semiconductor Inc ...
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... LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table LBPD2 LBPD1 LBPD0 Table 9 - Local Connection Memory in Block Programming Mode ZL50050 Source Stream No. Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] ...
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... Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The memory test result is monitored through the Memory BIST Register. 11.0 JTAG Port The ZL50050 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. 11.1 Test Access Port (TAP) The Test Access Port (TAP) consists of four input pins and one output pin described as follows: • ...
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... TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when not driven from an external source. This pin MUST be pulled low for normal operation. 11.2 TAP Registers The ZL50050 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an Instruction Register and three Test Data Registers. 11.2.1 Test Instruction Register The JTAG interface contains a four-bit instruction register ...
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... Diagram for Different Data Rates for the arrival order of the bits. Table 12 - Local Data Memory (LDM) Bits Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. ZL50050 Description Description 48 Zarlink Semiconductor Inc ...
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... Local Output Enable Bit When LOW, the channel may be high impedance, either at the device output, or set by an external buffer dependent upon the LORS pin. When HIGH, the channel is active. Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching ZL50050 Description Description 49 Zarlink Semiconductor Inc. ...
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... The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-15) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50050 Description Description 50 Zarlink Semiconductor Inc ...
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... When HIGH, the channel is active. 12:9 BSAB[3:0] Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. Table 17 - BCM Bits for 32 Mbps Source-to-Backplane Switching ZL50050 Description Description 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane BER Start Receive Register, BBSRR H 00CC Backplane BER Count Register, BBCR H 00CD - 00DC Local Input Bit Rate Register 0 - 15, LIBRR0 - 00ED - 00FC Local Output Bit Rate Register 0 - 15, LOBRR0 - Table 18 - Address Map for Registers (A14 = 0) ZL50050 Description Register 52 Zarlink Semiconductor Inc. Data Sheet ...
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... When LOW, Local streams LSTi0-15 and LSTo0-15 can be individually programmed for data rates Mbps. When HIGH, Local streams LSTi0-7 and LSTo0-7 operate at 32.768 Mbps only and LSTi8-15 and LSTo8-15 are unused. ZL50050 Register Description , the Frame Boundary Discriminator can handle both low ...
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... Local Connection Memory (LCM) for read or write operations. 01 selects Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 19 - Control Register Bits (continued) ZL50050 Description ODE Pin OSB bit BSTo0-15, LSTo0-15 ...
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... ZL50050 (a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (c) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... FP8i (g) Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 23 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50050 Frame Boundary 56 Data Sheet ...
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... Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 µs, upon completion of programming. Set LOW to abort the programming operation. Table 20 - Block Programming Register Bits ZL50050 Description 57 Zarlink Semiconductor Inc. Data Sheet ...
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... Clear Bit Error Rate Register for Local A LOW to HIGH transition resets the Local internal bit error counter and the Local Bit Error Register (LBERR) to zero. Table 21 - Bit Error Rate Test Control Register (BERCR) Bits ZL50050 Description selected for the Backplane port. ...
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... LCDRn Bit (where for Local Non-32 Mbps Mode for Local 32 Mbps Mode) 15:9 Reserved 8:0 LCD[8:0] Table 22 - Local Input Channel Delay Register (LCDRn) Bits ZL50050 Description Reset Name Value 0 Reserved Must be set to 0 for normal operation 0 Local Channel Delay Register The binary value of these bits refers to the channel delay value for the Local input stream ...
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... Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels Table 23 - Local Input Channel Delay (LCD) Programming Table ZL50050 Corresponding Delay Bits LCD8-LCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... 1 1111 1101 1 1111 1110 ...
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... Table 25 illustrates the bit delay and sampling point selection. LIDn LID4 LID3 LID2 Table 25 - Local Input Bit Delay and Sampling Point Programming Table ZL50050 1 / bit. 4 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Input Bit Delay Register ...
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... Table 25 - Local Input Bit Delay and Sampling Point Programming Table (continued) ZL50050 SMPL_MODE = LOW Input Data Input Data LID0 Bit Delay Bit Delay 3/4 ...
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... Channel (Default) 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... 509 Channels 510 Channels 511 Channels Table 27 - Backplane Input Channel Delay (BCD) Programming Table ZL50050 Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation BCD[8:0] 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream ...
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... The BIDR0 to BIDR15 registers are configured as follows: BIDRn Bit (where for Name Backplane Non-32 Mbps Mode for Backplane 32 Mbps Mode) 15:5 Reserved 4:0 BID[4:0] Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits ZL50050 1 / bit. 4 Reset Description Value 0 Reserved Must be set to 0 for normal operation 0 ...
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... Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table ZL50050 3 / bit periods forward, with resolution bit location bit increments SMPL_MODE = LOW ...
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... When the advancement is 0, the serial output stream has the normal alignment with the generated frame pulse FP8o. Local Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) Table 31 - Local Output Advancement (LOAR) Programming Table ZL50050 SMPL_MODE = LOW Input Data BID1 BID0 Bit Delay 1 ...
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... Backplane Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz 0 (Default) -2 cycles (~15 ns) -4 cycles (~31 ns) -6 cycles (~46ns) Table 33 - Backplane Output Advancement (BOAR) Programming Table ZL50050 Local Output Advancement For 32 Mbps Clock Rate 131.072 MHz -2 cycles (~15 ns) -3 cycles (~23 ns) Reset Name ...
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... Name 15:13 Reserved 12:9 LBSSA[3:0] 8:0 LBSCA[8:0] Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode ZL50050 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local BER Send Stream Address Bits The binary value of these bits refers to the Local output stream which carries the BER data ...
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... Table 37 - Local Receive BER Length Register (LRXBLR) Bits ZL50050 Description Description Reserved Must be set to 0 for normal operation Local Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver. (i.e., Total Channels ...
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... Bit Name Value 15:0 LBC[15:0] 0 Table 40 - Local BER Count Register (LBCR) Bits ZL50050 Description Reserved Must be set to 0 for normal operation Local BER Receive Stream Address Bits The binary value of these bits refers to the Local input stream configured to receive the BER data. ...
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... The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e., Total Channels = BTXBL value + 1) Table 42 - Backplane Transmit BER Length (BTXBLR) Bits ZL50050 Description Reserved Must be set to 0 for normal operation Backplane BER Send Stream Address Bits The binary value of these bits refers to the Backplane output stream which carries the BER data ...
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... BBRSA[4:0] 0 8:0 BBRCA[8:0] 0 Table 44 - Backplane BER Start Receive Register (BBSRR) Bits ZL50050 Description Reserved Must be set to 0 for normal operation Backplane Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver. (i.e., Total Channels = ...
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... Table 47 - Local Input Bit Rate (LIBR) Programming Table ZL50050 Description Backplane Bit Error Rate Count The binary value of these bits defines the Backplane Bit Error count. If the number of errors exceeds the maximum counter value, this counter will stay at FFFF until the CBERB bit in the BERCR register clears it ...
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... The BIBRR registers are configured as follows: BIBRn Bit Name (for 15) 15:2 Reserved 1:0 BIBR[1:0] Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits ZL50050 Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Output Bit Rate LOBR1 LOBR0 Bit rate for stream n ...
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... BOBRn Bit Name (for 15) 15:2 Reserved 1:0 BOBR[1:0] Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits MODE32B Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table ZL50050 BIBR1 BIBR0 Bit rate for stream Mbps Mbps Mbps 1 1 ...
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... Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 54 - Memory BIST Register (MBISTR) Bits ZL50050 Description 76 Zarlink Semiconductor Inc. Data Sheet ...
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... The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 55 - Device Identification Register (DIR) Bits ZL50050 Description 0 Reserved Will be set normal operation 0000 Revision Control Bits 0 Reserved Will be set normal operation 010 Device ID 77 Zarlink Semiconductor Inc ...
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... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Operating Temperature 2 Positive Supply 3 Positive Supply 4 Positive Supply 5 Input Voltage 6 Input Voltage Tolerant Inputs Voltages are with respect to ground (V ) unless otherwise stated. SS ZL50050 Symbol Min. V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V ...
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... Output Low Voltage High-Impedance Leakage Output Pin Capacitance S Voltages are with respect to ground (V ) unless otherwise stated. ss Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V) ZL50050 Sym. Min. Typ. Max DD_Core I 240 290 DD_Core I 100 ...
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... Clock Period, and using mid-bit sampling) 9 Output Frame Boundary Offset 10 FP8o Frame Pulse Width 11 FP8o Output Delay (from frame pulse edge to output frame boundary) 12 FP8o Output Delay (from output frame boundary to frame pulse edge) ZL50050 Sym. Level Units V 0.5V V 3.0V < DD_IO V 0.7V V 3.0V < ...
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... FP16o Output Delay (from output frame boundary to frame pulse edge) 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low 23 C16o Clock Rise/Fall Time ZL50050 Sym. Min. Typ. t 117 122 OCP8 OCH8 t 58 ...
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... Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 24 - Input and Output Clock Timing Diagram for ST-BUS ZL50050 t IFPW244 t ...
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... Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the Control Register. Figure 25 - Input and Output Clock Timing Diagram for GCI-Bus ZL50050 t IFPW244 t ...
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... Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay ZL50050 Sym. Min. Typ. Max IDS32 IDS16 t IDS8 ...
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... Bit1 Bit0 8.192 Mbps Ch127 Ch127 L/BSTo0-15 Bit0 4.096 Mbps Ch63 L/BSTo0-15 Bit0 2.048 Mbps Ch31 Note * : CK_int is the internal clock signal of 131.072 MHz Figure 26 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) ZL50050 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 ...
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... Bit1 16.384 Mbps Ch255 FP8o C8o CK_int * L/BSTo0-7 Bit1 Bit1 32.768 Mbps Ch511 Ch511 L/BSTo0-15 16.384 Mbps Note *: CK_int is the internal clock signal of 131.072 MHz Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) ZL50050 t IDS32 t SIS32 t SIH32 IDS16 t SIS16 t ...
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... Bit6 Bit7 Ch127 Ch127 8.192 Mbps L/BSTo0-15 Bit7 Ch63 4.096 Mbps L/BSTo0-15 Bit7 2.048 Mbps Ch31 Note *: CK_int is the internal clock signal of 131.072 MHz Figure 28 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) ZL50050 t IDS8 t SIS8 t SIH8 IDS4 t SIS4 ...
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... Ch255 FP8o C8o CK_int * L/BSTo0-7 Bit5 Bit6 32.768 Mbps Ch511 Ch511 L/BSTo0-15 Bit7 Ch255 16.384 Mbps Note *: CK_int is the internal clock signal of 131.072 MHz Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) ZL50050 t IDS32 t SIS32 t SIH32 IDS16 t SIS16 t SIH16 ...
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... High-Z to Active 2 Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured by pulling to the appropriate rail with R CLK STo STo Figure 30 - Serial Output and External Control ODE ZL50050 Sym. Min. Typ. Max ...
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... MHz 13 2 MHz 14 4 MHz ZL50050 16.384 Mbps Data Rate 32.768 Mbps Data Rate Jitter Tolerance Jitter Tolerance 1200 1200 150 110 Zarlink Semiconductor Inc ...
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... Note: There must be a minimum between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a minimum must separate the de-assertion of DTA (to high) and the assertion of CS and/ initiate the next access R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 32 - Motorola Non-Multiplexed Bus Timing ZL50050 Sym. Min. Typ. Max CSS t 9 RWS t ...
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... TDi Input Hold Time 8 TDo Output Delay 9 TRST pulse width †Characteristics are over recommended operating conditions unless otherwise stated. TCK t TMSS TMS t TDIS TDi TDo TRST Figure 33 - JTAG Test Port Timing Diagram ZL50050 Sym. Min. Typ. t 100 TCKP t 80 TCKH t 80 TCKL t 10 TMSS ...
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... TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD BOTTOM VIEW SIDE VIEW Previous package codes: DIMENSION ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...