zl50058 Zarlink Semiconductor, zl50058 Datasheet
zl50058
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zl50058 Summary of contents
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... K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion ( 16 Mbps), and 48 Inputs and 48 Outputs Ordering Information ZL50057GAC ZL50058GAC ZL50058GAG2 **Pb Free Tin/Silver/Copper 4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any combination fixed allocation of 8 input and 8 output streams at 32.768 Mbps • ...
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... Note 1: For software compatibility between ZL50057 and MT90870, please refer to Section 2.6. Applications • Central Office Switches (Class 5) • Media Gateways • Class-independent switches • Access Concentrators • Scalable TDM-Based Architectures • Digital Loop Carriers ZL50057 Zarlink Semiconductor Inc. Data Sheet ...
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... Device Overview The ZL50057 and ZL50058 are two different packages of the same device. The ZL50057/8 has two data ports, the Backplane and the Local port. The Backplane port has two independent modes of operation, either 32 input and 32 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any combination input and 16 output streams operated at 32 ...
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... Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1 Local Connection Memory 9.2 Backplane Connection Memory 9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.1 Test Access Port (TAP ZL50057/8 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Bit Rate Registers (LOBRR0 - LOBRR15 14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR31 14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR31 14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ZL50057/8 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50057/8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50057 PBGA Connections (272 PBGA, 27mm x 27mm) Pin Diagram (as viewed through top of package Figure 3 - ZL50058 PBGA Connections (256 PBGA, 17mm x 17mm) Pin Diagram (as viewed through top of package Figure 4 - 12,288 x 12,288 Channels (16Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5 - 8,192 x 4,096 Channels (16Mbps), bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6 - 6,144 by 6,144 Channels Non-Blocking Bi-directional Configuration ...
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... Table 44 - Backplane Transmit BER Length (BTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 45 - Backplane Receive BER Length (BRXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 46 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 47 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 48 - Local Input Bit Rate Register (LIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ZL50057/8 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 52 - Backplane Input Bit Rate Register (BIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 54 - Backplane Output Bit Rate Register (BOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 55 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 56 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 57 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ZL50057/8 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... IC_GND NC C8o IC_GND IC_GND C8i C16o VDD_ D5 D1 IC_GND VDD_ IC_ IC_ CORE CORE OPEN OPEN (as viewed through top of package) 9 Zarlink Semiconductor Inc. Data Sheet TCK BCSTo1 NC LSTo0 LSTo1 LSTo2 NC TRST BCSTo2 NC IC_GND LSTo3 LSTo4 LSTo5 BCSTo0 BCSTo3 LCSTo1 LCSTo0 ...
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... BSTi11 VDD_IO N BSTi12 BSTi13 BSTi14 BSTi15 P BSTi17 BSTi18 BSTi19 BSTi20 R BSTi22 BSTi23 BSTi24 BSTi25 T BSTi27 BSTi28 BSTi29 BSTi30 Figure 3 - ZL50058 PBGA Connections (256 PBGA mm) Pin Diagram ZL50057 R/W CS BCSTo0 BCSTo1 BCSTo2 BCSTo3 ODE ...
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... U14 C8o V13 FP8o V14 C16o W13 ZL50057/8 ZL50058 Package (256-ball PBGA) T10 Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192 MHz clock. The internal frame boundary is aligned with the clock falling or rising edge, as controlled by the C8IPOL bit in the Control Register. Input data on both the ...
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... U1, W1, W2, R1, R2, R3, W3, Y1, Y2, R4, R5, T1, U5, V4, W4, T2, T3, T4 ZL50057/8 ZL50058 Package (256-ball PBGA) P11 Frame Pulse Output (5 V Tolerant Three-state Output). When the Frame Pulse Width bit (FPW) of the Control Register is LOW (default), this pin outputs a 61 ns-wide frame pulse ...
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... LSTi8-15 N19, N20, P17, P19, P20, R18, R19, R20 Backplane and Local Outputs and Control ODE A12 ZL50057/8 ZL50058 Package (256-ball PBGA) K13, K14, Local Serial Input Streams Tolerant Inputs with K15, K16, Internal Pull-downs). L13, L14, In Local Non-32 Mbps Mode, these pins accept serial TDM ...
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... C3, C4, D1, C1, C2, D1, D2, D3, D4, D2, D3, E1, E1, E2, E3 ZL50057/8 ZL50058 Package (256-ball PBGA) D5 Backplane Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the BSTo0-31 outputs driven high, and the BCSTo0-3 outputs driven low ...
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... J1, J2, J3, J4 BCSTo0-3 C14, A15, A9, A10, A11, B15, C15 A12 ZL50057/8 ZL50058 Package (256-ball PBGA) Backplane Serial Output Streams Tolerant, Three-state Outputs with Slew-Rate Control). In Backplane Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16 ...
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... A19, B18, B15, B16, B19, B20, C13, C14, C18, C19 C15, C16 ZL50057/8 ZL50058 Package (256-ball PBGA) Local Output Reset State (5 V Tolerant Input with Internal Pull-down). When this input is LOW, the device will initialize with the LSTo0-15 outputs driven high, and the LCSTo0-1 outputs driven low ...
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... C8, B8, A8, B6, B7, B8, D9, B9, A9, B9, C5, C6, D10, C10, C7, C8, C9 A10 ZL50057/8 ZL50058 Package (256-ball PBGA) Local Serial Output Streams Tolerant Three-state Outputs with Slew-Rate Control). In Local Non-32 Mbps Mode, these pins output serial TDM data streams at a data rate of: 16 ...
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... C11 A7 DTA A13 C10 RESET C12 B11 ZL50057/8 ZL50058 Package (256-ball PBGA) Data Bus Tolerant Inputs/Outputs with Slew-Rate Control). These pins form the 16-bit data bus of the microprocessor port LSB Chip Select (5 V Tolerant Input). Active LOW input used by the microprocessor to enable the microprocessor port access ...
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... Y7, Y11, Y14 L10, L11 V U12 M10 DD_PLL ZL50057/8 ZL50058 Package (256-ball PBGA) Test Clock (5 V Tolerant Input). Provides the clock to the JTAG test logic. Test Mode Select (5 V Tolerant Input with Internal Pull-up). JTAG signal that controls the state transitions of the TAP controller ...
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... IC_GND A2, B17, C3, D6, D7, D8, D16, V11, D9, T6, T7, W10, W11, T8, T9 Y10 ZL50057/8 ZL50058 Package (256-ball PBGA) Ground. No Connects. These pins are not used and can be tied HIGH, LOW, or left unconnected. Internal Connections - OPEN. These pins must be left unconnected. Internal Connections - GND. These pins must be tied LOW. ...
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... Mbps, in conjunction with the Backplane streams (BSTi0-31 and BSTo0-31) operating at 16.384 Mbps (Backplane Non-32 Mbps Mode conjunction with the Backplane streams (BSTi0-15 and BSTo0-15) operating at 32.768 Mbps (Backplane 32 Mbps Mode). ZL50057/8 BSTo0-31 32 streams LSTo0-15 16 streams ZL50057/8 LSTo0-15 16 streams LSTi0-15 16 streams ZL50057/8 21 Zarlink Semiconductor Inc. Data Sheet OUTPUT LOCAL ...
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... Backplane input to Backplane output streams • 4,096-channel x 4,096-channel non-blocking switching from Local input to Local output streams ZL50057/8 ZL50057 Total 24 input streams and 24 output streams 22 Zarlink Semiconductor Inc. Data Sheet LSTi0-15 BSTi24-31 LSTo0-15 BSTo24-31 ...
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... If the Backplane 32Mbps Mode is selected by setting the Control Register bit MODE32B HIGH, the settings in BIBRRn and BOBRRn are ignored. Similarly, if the Local 32Mbps Mode is selected by setting the Control Register bit MODE32L HIGH, the settings in LIBRRn and LOBRRn are ignored. ZL50057/8 23 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps in Local Non-32 Mbps Mode. Unused in Local 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps Mode. All streams at 32.768 Mbps in Backplane 32 Mbps Mode. 2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps Mode. Unused in Backplane 32 Mbps Mode. 24 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Output Bit Rate Register (BOBRR0-31). The Backplane streams can also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 16 output streams, BSTo0-15, operate at 32.768 Mbps and the remaining 16 streams, BSTo16-31, will not be used and must be connected to a defined logic level. ZL50057/8 25 Zarlink Semiconductor Inc. Data Sheet ...
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... The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072 MHz. ZL50057/8 26 Zarlink Semiconductor Inc. Data Sheet ...
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... Channel Channel Channel Channel 0 6 Channel 0 1 Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 510 Channel 511 Channel 510 Channel 511 ...
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... B 28 Zarlink Semiconductor Inc. Data Sheet CH2 CH3 CH4 CH5 CH7 CH8 ...
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... Control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame boundary with respect to the master frame pulse, FP8i. The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere within a frame to a resolution of 1/4 of the bit period. ZL50057/8 29 Zarlink Semiconductor Inc. Data Sheet ), B ...
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... Channel Delay, 2 Ch127 Ch0 Ch126 operation) 30 Zarlink Semiconductor Inc. Data Sheet Ch126 Ch127 Ch125 Ch126 ...
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... Bit Delay, 1 Ch0 Ch255 Ch255 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 2 1 ...
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... ZL50057/8 Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 3/4 point Ch127 Ch0 sample at 2/4 point Data Rate of 8 Mbps 32 Zarlink Semiconductor Inc. Data Sheet ...
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... Connection Memory bit Zarlink Semiconductor Inc. Data Sheet Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 4 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Bit 4 LSTo0-15/ LCSTo0-1/ BSTo0-31 BCSTo0-3 HIGH LOW HI-Z LOW HIGH ...
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... With stream LSTo4 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1 will be transmitted during the C16o clock period numbers 9 and 17. ZL50057/8 LE/BE OSB (Local / LORS/BORS (Control Backplane (input pin) Connection Memory bit Zarlink Semiconductor Inc. Data Sheet LSTo0-15/ LCSTo0-1/ BSTo0-31 BCSTo0-3 HI-Z LOW ACTIVE ACTIVE (HIGH or LOW) (HIGH or LOW) ...
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... Ch 254 Ch 127 254 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 Zarlink Semiconductor Inc. Data Sheet 2 Mbps Frame Ch 0 Boundary ...
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... 3 etc. etc. (continued) 36 Zarlink Semiconductor Inc. Data Sheet 2 2 Mbps ...
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... Figure 13 - Local Port External High Impedance Control Bit Timing (Non-32 Mbps Mode) ZL50057 Chan 0 Chan 0 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 Channel 0 Bit 7 37 Zarlink Semiconductor Inc. Data Sheet Channel 255 Chan 127 Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 ...
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... For stream LSTo2, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock period no. 2036 on LCSTo0. 4. For stream LSTo3, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock period no LCSTo1. ZL50057/8 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 4 - LCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) Zarlink Semiconductor Inc. ZL50057/8 2 Channel No. LCSTo1 32 Mbps 3 ...
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... Ch 511 511 3 3-2 3 etc. etc. etc. (continued) 40 Zarlink Semiconductor Inc. Data Sheet 2 Frame Boundary ...
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... ZL50057/8 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 One C16o cycle 41 Zarlink Semiconductor Inc. Data Sheet Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 ...
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... Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48. 4. With stream BSTo8 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1 will be transmitted during the C16o clock period nos. 9 and 17. ZL50057/8 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Ch 254 254 255 255 255 255 43 Zarlink Semiconductor Inc. Data Sheet 2 Channel No ...
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... etc. etc. etc. (continued) 44 Zarlink Semiconductor Inc. Data Sheet 2 Channel No. Ch 127 127 127 127 ...
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... Figure 15 - Backplane Port External High Impedance Control Bit Timing (Non-32 Mbps Mode) ZL50057 Chan 0 Chan 0 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 Channel 0 Bit 7 45 Zarlink Semiconductor Inc. Data Sheet Channel 255 Chan 127 Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 ...
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... For stream BSTo4, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock period number 2036 on BCSTo0. 4. For stream BSTo5, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock period number 12 on BCSTo1. ZL50057/8 46 Zarlink Semiconductor Inc. Data Sheet ...
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... Ch 509 509 510 510 510 510 47 Zarlink Semiconductor Inc. Data Sheet Frame Ch 2 Boundary ...
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... Zarlink Semiconductor Inc. Data Sheet 2 Channel No. 32 Mbps Ch 511 Ch 511 Ch 511 Ch 511 Frame Ch 2 Boundary etc. ...
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... ZL50057/8 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 49 Zarlink Semiconductor Inc. Data Sheet Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 One C16o cycle ...
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... Number (n) 2 Mbps Mbps Mbps 0 to 127 16 Mbps 0 to 255 32 Mbps 0 to 511 Input Channel Delay frames - α Table 9 - Data Throughput Delay 50 Zarlink Semiconductor Inc. Data Sheet 127 0 to 255 0 to 511 ...
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... Frame N+1 Frame N+2 Frame N+3 Frame N+1Data Frame N+2 Data Frame N+3 Data 2 Frames + ( Frame N-1 Data Frame N Data Frame N+1 Data Output Ch0 51 Zarlink Semiconductor Inc. Data Sheet Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+2 Data Frame N+3 Data Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+2 Data ...
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... Input Channel Delay (from 1 to max # of channels) Frame N Data Frame N+1 Data Frame N+2 Data 3 Frames - α Frame N-2 Data Frame N-1 Data Frame N Data Output Ch0 52 Zarlink Semiconductor Inc. Data Sheet Frame N+4 Frame N+5 Frame N+3 Data Frame N+4 Data Frame N+4 Data Frame N+1 Data Frame N+2 Data Frame N+4 ...
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... Message Mode bits, LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The per-channel enable bits (LE ZL50057 ...... ..... ..... ..... 254 ...... ..... ..... ..... 254 3 ..... ..... 1 2 ...... ..... 254 53 Zarlink Semiconductor Inc. Data Sheet 255 255 0 2 255 Channels containing unknown data ...
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... RESET pin; this delay is required for determination of the input frame pulse format. ZL50057/8 supply (nominally +3 established before the DD_IO supplies (nominally +1.8 V). The V DD_PLL supply by more than 0.3 V. DD_IO 54 Zarlink Semiconductor Inc. Data Sheet and V supplies may be DD_CORE ...
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... Table 10. In Message Mode (bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that the output channel is not tri-stated. ZL50057/8 RESET de-assertion Figure 24 - Hardware RESET De-assertion 55 Zarlink Semiconductor Inc. Data Sheet ...
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... Bits[12:8] legal values 0:31 Bits[12:9] legal values 0: Zarlink Semiconductor Inc. Data Sheet Source Channel No. Bits[7:0] legal values 0:31 Bits[7:0] legal values 0:63 Bits[7:0] legal values 0:127 Bits[7:0] legal values 0:255 Bits[8:0] legal values 0:511 ...
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... Depending on the previously applied sequence to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the ZL50057 Zarlink Semiconductor Inc. Data Sheet ...
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... Version, Bits <31:28>:0000 Part No., Bits <27:12>:1100 0011 1000 1001 Manufacturer ID, Bits <11:1>:0001 0100 101 Header, Bit <0> (LSB):1 11.3 Boundary Scan Description Language (BSDL) File A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface. ZL50057 Zarlink Semiconductor Inc ...
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... Diagram for Different Data Rates for the arrival order of the bits. Table 14 - Local Data Memory (LDM) Bits Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the table above are presented to provide 16-bit microprocessor read accesses. ZL50057/8 Description Description 59 Zarlink Semiconductor Inc. Data Sheet ...
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... When HIGH, the channel is active. 12:8 LSAB[4:0] Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when LMM is set HIGH. Table 16 - LCM Bits for Non-32 Mbps Source-to-Local Switching ZL50057/8 Description Description 60 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-31) in place of data defined by the Source Control, Stream and Channel Address bits. ZL50057/8 Description Description 61 Zarlink Semiconductor Inc. Data Sheet ...
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... When HIGH, the channel is active. 12:9 BSAB[3:0] Source Stream Address Bits The binary value of these 4 bits represents the input stream number. Ignored when BMM is set HIGH. Table 19 - BCM Bits for 32 Mbps Source-to-Backplane Switching ZL50057/8 Description Description 62 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane BER Start Receive Register, BBSRR H 00CC Backplane BER Count Register, BBCR H 00CD - 00DC Local Input Bit Rate Register 0 - 15, LIBRR0 - 00ED - 00FC Local Output Bit Rate Register 0 - 15, LOBRR0 - Table 20 - Address Map for Registers (A14 = 0) ZL50057/8 Description Register 63 Zarlink Semiconductor Inc. Data Sheet ...
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... When HIGH, Local streams LSTi0-7 and LSTo0-7 operate at 32.768Mbps only and LSTi8-15 and LSTo8-15 are unused. ZL50057/8 Register Description , the Frame Boundary Discriminator can handle both low B , the Frame Boundary Discriminator is set to handle lower B Table 21 - Control Register Bits 64 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Connection Memory (BCM) for read or write operations. 10 selects Local Data Memory (LDM) for read-only operation. 11 selects Backplane Data Memory (BDM) for read-only operation. Table 21 - Control Register Bits (continued) ZL50057/8 Description ODE Pin OSB bit BSTo0-31, LSTo0- Zarlink Semiconductor Inc. Data Sheet Disabled Disabled Enabled ...
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... Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (d) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 25 - Frame Boundary Conditions, ST-BUS Operation Zarlink Semiconductor Inc. Frame Boundary 66 Data Sheet ...
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... FP8i (g) Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (h) Pulse Width = 244ns, Control Register B it8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 26 - Frame Boundary Conditions, GCI-Bus Operation Zarlink Semiconductor Inc. ZL50057/8 Frame Boundary 67 Data Sheet ...
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... Block Programming Enable A LOW to HIGH transition of this bit enables the Memory Block Programming function. A LOW will be returned after 125 µs, upon completion of programming. Set LOW to abort the programming operation. Table 22 - Block Programming Register Bits ZL50057/8 Description 68 Zarlink Semiconductor Inc. Data Sheet . ...
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... A LOW to HIGH transition resets the Local internal bit error counter and the Local Bit Error Register (LBERR) to zero. Table 23 - Bit Error Rate Test Control Register (BERCR) Bits ZL50057/8 Description selected for the Backplane selected for the Backplane 69 Zarlink Semiconductor Inc. Data Sheet ...
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... Must be set to 0 for normal operation 0 Local Channel Delay Register The binary value of these bits refers to the channel delay value for the Local input stream. 70 Zarlink Semiconductor Inc. Data Sheet selected for the Local port selected for the Local port. ...
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... Channels 510 Channels 511 Channels Table 25 - Local Input Channel Delay (LCD) Programming Table ZL50057/8 Corresponding Delay Bits LCD8-LCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... 1 1111 1101 1 1111 1110 1 1111 1111 71 Zarlink Semiconductor Inc. Data Sheet ...
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... SMPL_MODE = LOW Input Data LID1 LID0 Bit Delay (Default) 72 Zarlink Semiconductor Inc. Data Sheet Description LID[4: LID[4: SMPL_MODE = HIGH Input Data Input Data Sampling ...
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... Zarlink Semiconductor Inc. Data Sheet SMPL_MODE = HIGH Input Data Sampling Point 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 3/4 4/4 1/4 2/4 ...
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... Must be set to 0 for normal operation BCD[8:0] 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream. Corresponding Delay Bits 74 Zarlink Semiconductor Inc. Data Sheet Description BCD8-BCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 ...
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... When SMPL_MODE = LOW, the binary value of these bits refers to the input bit fractional delay value ( When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point ( refers to the integer bit delay value ( bits). 75 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor Inc. Data Sheet 1 / bit period. The BID[4: SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 0 (Default) 3/4 0 4/4 0 1/4 0 2/4 ...
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... Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation LOA[1:0] 0 Local Output Advancement Value 77 Zarlink Semiconductor Inc. Data Sheet SMPL_MODE = HIGH Input Data Input Data Sampling Bit Delay Point 6 3/4 6 4/4 6 1/4 6 2/4 7 3/4 7 4/4 7 1/4 7 2/4 ...
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... Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) -2 cycles (~15 ns) -3 cycles (~23 ns) Reset Name Value Reserved 0 Reserved Must be set to 0 for normal operation BOA[1:0] 0 Backplane Output Advancement Value 78 Zarlink Semiconductor Inc. Data Sheet Corresponding Advancement Bits LOA1 LOA0 Description ...
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... Table 35 - Backplane Output Advancement (BOAR) Programming Table ZL50057/8 Backplane Output Advancement For 32 Mbps Clock Rate 131.072 MHz 0 (Default) -1 cycle (~7.6 ns) -2 cycles (~15 ns) -3 cycles (~23 ns) 79 Zarlink Semiconductor Inc. Data Sheet Corresponding Advancement Bits BOA1 BOA0 ...
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... The binary value of these bits refers to the Local output stream which carries the BER data. 0 Local BER Send Channel Address Bits The binary value of these bits refers to the Local output channel at which the BER data starts to be sent. 80 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Description Reserved Must be set to 0 for normal operation Local Receive BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Receiver. (i.e., Total Channels = LRXBL value + 1) 81 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Bit Error Rate Count The binary value of the bits defines the Local Bit Error count. If the number of errors exceeds the maximum counter value, this counter will stay at FFFF until the CBERL bit in the BERCR register clears it Zarlink Semiconductor Inc. Data Sheet ...
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... Description Reserved Must be set to 0 for normal operation Backplane Transmit BER Length Bits The binary value of these bits defines the number of channels in addition to the Start Channel allocated for the BER Transmitter. (i.e., Total Channels = BTXBL value + 1) 83 Zarlink Semiconductor Inc. Data Sheet ...
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... The binary value of these bits refers to the Backplane input stream configured to receive the BER data. Backplane BER Receive Channel Address Bits The binary value of these bits refers to the Backplane input channel at which the BER data starts to be compared. 84 Zarlink Semiconductor Inc. Data Sheet ...
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... CBERB bit in the BERCR register clears it. H Reset Value 0 Reserved Must be set to 0 for normal operation 0 Local Input Bit Rate LIBR1 LIBR0 Bit rate for stream Zarlink Semiconductor Inc. Data Sheet Description 2 Mbps 4 Mbps 8 Mbps 16 Mbps 32 Mbps ...
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... Local Output Bit Rate LOBR1 LOBR0 Bit rate for stream Mbps Mbps Mbps Mbps Mbps Reset Value 0 Reserved Must be set to 0 for normal operation 0 Backplane Input Bit Rate 86 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Mbps Mbps Mbps Reset Value 0 Reserved Must be set to 0 for normal operation 0 Backplane Output Bit Rate BOBR1 BOBR0 Bit rate for stream Mbps Mbps Mbps Mbps Mbps 87 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Backplane Connection Memory Pass/Fail Bit (Read-only) This bit indicates the Pass/Fail status following completion of the Backplane Connection Memory BIST sequence (indicated by assertion of BISTCCB). A HIGH indicates Pass, a LOW indicates Fail. Table 56 - Memory BIST Register (MBISTR) Bits ZL50057/8 Description 88 Zarlink Semiconductor Inc. Data Sheet ...
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... The DIR register is configured as follows: Bit Name Reset Value 15:8 Reserved 7:4 RC[3:0] 3 Reserved 2:0 DID[2:0] Table 57 - Device Identification Register (DIR) Bits ZL50057/8 Description 0 Reserved Will read 0 in normal operation 0000 Revision Control Bits 0 Reserved Will read 0 in normal operation 001 Device ID 89 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Min. V -0.5 DD_CORE V -0.5 DD_IO V -0.5 DD_PLL V -0 -0.5 I_5V Sym. Min. Typ 3.0 3.3 DD_IO V 1.71 1.8 DD_CORE V 1.71 1.8 DD_PLL I_5V 90 Zarlink Semiconductor Inc. Data Sheet Max. Units 2.5 V 5 +0.5 V DD_IO 7 1.5 W °C +125 Max. Units °C +85 3.6 V 1. DD_IO 5.5 V ...
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... BL I 200 PU I 200 2 0 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions mA Static I and DD_Core PLL current mA Applied clock C8i = 8.192 MHz µA Static I DD_IO mA I with all output AV streams at max. data rate unloaded V V µ ...
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... FPFBF8_244 FPFBF8_122 t 117 122 FBFPF8_244 FBFPF8_122 t 117 122 OCP8 OCH8 OCL8 rOC8 fOC8 92 Zarlink Semiconductor Inc. Data Sheet Conditions < 3.6V DD_IO < 3.6V DD_IO < 3.6V DD_IO Max. Units Notes 350 ns 220 110 ns 60 110 ns 60 124 7.0 ns ...
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... FPFBF16_122 FPFBF16_61 FBFPF16_122 FBFPF16_61 OCP16 OCH16 OCL16 rOC16 t fOC16 93 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 127 ns FPW =1 FPW =60pF FPW =1 FPW FPW =1 FPW =60pF ...
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... Figure 27 - Input and Output Clock Timing Diagram for ST-BUS ZL50057/8 t IFPW244 t IFPH244 t IFPW122 t t IFPS122 IFPH122 t t ICH ICP t rIC t OFBOS t OFPW8_244 t FBFPF8_244 t OFPW8_122 t t FBFPF8_122 FPFBF8_122 t t OCH8 OCP8 t rOC8 t OFPW16_122 t t FPFBF16_122 FBFPF16_122 t OFPW16_61 t FBFP16_61 t rOC16 94 Zarlink Semiconductor Inc. Data Sheet t fIC t fOC8 t OCP16 t fOC16 ...
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... Figure 28 - Input and Output Clock Timing Diagram for GCI-Bus ZL50057/8 t IFPW244 t IFPS244 t IFPW122 t t IFPS122 IFPH122 t t ICH ICP t rIC t OFBOS t OFPW8_244 t FPFBF8_244 t OFPW8_122 t t FBFPF8_122 FPFBF8_122 t t OCP8 OCH8 t rOC8 t OFPW16_122 t t FPFBF16_122 FBFPF16_122 t OFPW16_61 t FBFP16_61 t fOC16 95 Zarlink Semiconductor Inc. Data Sheet t IFPH244 t fIC t FBFPF8_244 t fOC8 t OCP16 t rOC16 ...
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... SIH2 t 7 9.5 OFBOS t 4.5 SOD32 t 4.5 SOD16 t 4.5 SOD8 t 4.5 SOD4 t 4.5 SOD2 96 Zarlink Semiconductor Inc. Data Sheet Units Notes ns With SMPL_MODE = 0 (3/4-bit sampling) and zero offset. ns With respect to Min. Input Data Sampling Point ns With respect to Max. Input Data Sampling Point =50pF L These numbers ...
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... OFBOS t SOD8 Bit7 Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Ch0 t SOD4 Bit7 Bit6 Ch0 Ch0 t SOD2 Bit7 Ch0 97 Zarlink Semiconductor Inc. Data Sheet Bit5 Bit4 Ch0 Ch0 Bit6 Ch0 Bit3 Bit2 Bit1 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit6 ...
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... SIS16 t SIH16 Bit7 Bit0 Ch0 Ch255 t OFBOS t SOD32 Bit7 Bit6 Bit5 Bit0 Ch0 Ch0 Ch0 Ch511 t SOD16 Bit0 Bit7 Ch255 Ch0 98 Zarlink Semiconductor Inc. Data Sheet Bit6 Bit5 Ch0 Ch0 Bit4 Bit2 Bit3 Ch0 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 ...
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... OFBOS t SOD8 Bit0 Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Ch0 t SOD4 Bit0 Bit1 Ch0 Ch0 t SOD2 Bit0 Ch0 99 Zarlink Semiconductor Inc. Data Sheet Bit2 Bit3 Ch0 Ch0 Bit1 Ch0 Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Bit2 Bit3 Ch0 Ch0 Bit1 ...
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... IDS16 t SIS16 t SIH16 Bit0 Ch0 t OFBOS t SOD32 Bit0 Bit1 Bit2 Bit7 Ch0 Ch0 Ch0 Ch511 t SOD16 Bit0 Ch0 100 Zarlink Semiconductor Inc. Data Sheet Bit1 Bit2 Ch0 Ch0 Bit3 Bit5 Bit4 Ch0 Ch0 Ch0 Bit2 Bit1 Ch0 Ch0 ...
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... DZ HiZ Valid Data t ZD HiZ Valid Data t t ODZ ODE Valid Data STo Hi-Z Hi-Z Figure 34 - Output Driver Enable (ODE) 101 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns R =1k, C =50pF, See Note =1k, C =50pF, See Note ...
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... MHz ZL50057/8 16.384 Mbps Data Rate 32.768 Mbps Data Rate Jitter Tolerance Jitter Tolerance 1200 1200 150 110 102 Zarlink Semiconductor Inc. Data Sheet Units 600 ns 600 ...
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... RDS 12 t 4.5 RDH t 9 WDS t 9 WDH t AKD AKH , with timing corrected to cancel time taken to discharge L 103 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Memory Read Register Read ns C =60pF =60pF Note 1 ...
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... D0-D15 READ D0-D15 WRITE DTA Figure 35 - Motorola Non-Multiplexed Bus Timing ZL50057/8 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t RDS t AKD 104 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH RDH WDH V ...
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... TCKP t 80 TCKH t 80 TCKL t 10 TMSS t 10 TMSH t 20 TDIS t 60 TDIH t TDOD t 200 TRSTW t t TCKL TCKH t TCKP t TMSH t TDIH t TDOD 105 Zarlink Semiconductor Inc. Data Sheet Max Units Notes =30pF TRSTW ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes: ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...