am79c981 Advanced Micro Devices, am79c981 Datasheet
am79c981
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am79c981 Summary of contents
Page 1
... The device integrates the Repeater functions specified by Section 9 of the IEEE 802.3 standard and Twisted-Pair Transceiver functions complying with the 10BASE-T standard. The Am79C981 provides eight integral twisted-pair medium attachment units (MAUs) and an attachment unit interface (AUI) port in an 84-pin plastic leaded chip carrier (PLCC) ...
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... V supply. TM User Manual Manchester RX MUX Decoder Phase = Locked Loop Control Manchester Encoder IMR+ Chip Control Partitioning Link Test Timers (HIMIB ) (ILACC ) Am79C981 FIFO TX Preamble MUX Jam Sequence FIFO Expansion Port Test and Management Port REQ ACK COL DAT JAM SI SO SCLK ...
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... PLCC IMR+ Chip Am79C981 Am79C981 RXD7– 73 TXD7+ 72 TXD7– TXP7+ 69 TXP7– TXD6+ 67 TXD6– TXP6+ 64 TXP6– ...
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... TXP– DI– RXD+ CI+ RXD– CI– Am79C981 DAT SCLK SI JAM SO ACK COL X2 REQ X1 CRS TEST STR RST AUI Repeater Expansion State Machine Twisted Pair Am79C981 Twisted Pair Ports (8 Ports) Expansion Port Port Activity Monitor 17306B-3 Port Port 7 17306B-4 ...
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... J = 84-Pin Plastic Leaded Chip Carrier (PL 084) SPEED Not Applicable Valid combinations list configurations planned to be sup- JC ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C981 Valid Combinations 1–75 ...
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... When ACK is not asserted, JAM is in high impedance. If REQ and ACK are both asserted, then JAM is an out- put. If ACK is asserted and REQ not asserted, then JAM is an input. This pin needs to be either pulled up or pulled down through a high-value resistor. Am79C981 . DD DV Pin # Function ...
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... Minimum mode. An inverted version of the RST signal can be used to program the device into the Minimum mode. Test Am79C981 SI SO Output TP Ports Receive Polarity Status + AUI 0 SQE Test Error Status 1 Bit Rate Error (all ports) TP Ports Link Status + AUI Loopback ...
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... X 20MHz CMOS clock signal can be used to drive this pin Crystal 2 Crystal Connection The internal clock generator uses a 20 MHz crystal at- tached to pins X 1 used, this pin should be left unconnected. Am79C981 and X . Alternatively, an external 1 2 and external clock source is 2 ...
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... FUNCTIONAL DESCRIPTION The Am79C981 Integrated Multiport Repeater Plus de- vice is a single chip implementation of an IEEE 802.3/Ethernet repeater (or hub). In addition to the eight integral 10BASE-T ports plus one AUI port comprising the basic repeater, the IMR+ chip also provides the hooks necessary for complex network management and diagnostics ...
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... Table 1 summarizes the state of the IMR+ chip following reset. Table 1. IMR+ Chip After Reset State After Reset HIGH LOW HIGH HI-IMPEDANCE LOW IDLE ENABLED STANDARD ALGORITHM STANDARD ALGORITHM ENABLED, TP PORTS IN LINK FAIL DISABLED Am79C981 Pull Up/Pull Down Either Pull Up* No Terminated N/A N/A N/A N/A ...
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... REQ1 & REQ2 & REQ3 & ....REQn + REQ1 & REQ2 & REQ3 & .... REQn + ACK & (REQ1 + REQ2 + REQ3 + ... REQn) COL = Above equations are in positive logic, i.e., a variable is true when asserted. A single PALCE16V8 will perform the arbitration func- tion for a repeater based on several IMR+ devices. Am79C981 AMD 1–81 ...
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... IMR+ devices on that module, and provides sig- nals to the backplane for use by a global arbiter. For more detailed information, see AMD’s IEEE 802.3 Repeater Technical Manual, PID# 17314A. Am79C981 Bus transceivers needed if DAT and JAM buses exceed 100 pF loading. ...
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... AMD’s IEEE 802.3 Repeater Technical Manual, PID# 17314A. Am7990 LANCE Am79C900 ILACC Am79C940 MACE or Am79C960 PCnet-ISA DONE_COUNT NEW96 Arbiter PALCE16V8 CDT IMR+2 RST X1 Figure 2. Expandable Modular Repeater Am79C981 AMD Interface PALCE16V8 RTSCLK CDT RCKEN ACKCLK IMR+n RST X1 17306B-6 14396C-033A 1–83 ...
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... Data bytes are received and transmitted LSB first and MSB last. See Table 2 for a summary of the manage- ment commands. STRT Management Command/Response Timing STRT D0 Am79C981 Results Phase Next Command 17306B-17 Next Command Execution Phase 17306B-18 ...
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... Am79C981 AMD SO Data PBSL 0000 C7...C0 E7...E0 L7...L0 P7...P0 M000 0000 XXXX 0001 PBSL 0000 PBSL 0000 PBSL 0000 ...
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... Jam Sequence on the AUI port. Issuing this command will also cause the AUI port to have its internal partitioning state machine forced to its idle state. Therefore, a Partitioned Port may be re- connected by first disabling and then re-enabling the port. Am79C981 00011111 None 00010000 None alternate ...
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... GET (Read) Opcodes AUI Port Status SI data: SO data: The combined AUI status allows a single instruction to be used for monitoring AUI port. The four status bits re- ported are: Am79C981 AMD 01010### None 01100### None 01110### None 10001111 PBSL0000 1– ...
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... IMR+ device transmit function has been transmitting continuously for more than 65536 Bit Times. The MJLP Status bit (M) is set this happens. This bit remains set and is only cleared when the MJLP status is read by using this command. Am79C981 10100000 E7...............E0 11010000 L7...............L0 ...
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... STR cycle. The rising edge of the X1 clock, occur- ring before falling edge of STR, is used to strobe in the state of the SI and SCLK pins. In this Minimum Mode, the Management Port mode is not active. To exit the Minimum mode, the IMR+ device must reset into the normal Management Port mode. Am79C981 AMD 1–89 ...
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... The accuracy of the CRS signals is 10 Bit Times (BT) (1 s). Specifically, a transition to active state by any of the internal carrier sense bits that lasts for less than 10BT is latched internally and is used to set the ap- propriate bit during the next sample period. Am79C981 TCK TCK CK SIPO ...
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... STR signal is not available when the IMR+ chip is attached to HIMIB device, and must be generated externally. Figure 5b. Port Activity Monitor Implementation (Continued) PRELIMINARY 1/2 ’74 TCK Q D TCK CK Q CLR X1 CRS Am79C981 X2 IMR+ Chip RST STR AUI TP0 TP1 Am79C981 AMD Shift Register CK SIPO SI CK Register Carrier Sense Outputs ...
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... Therefore, any signal distortion present on the re- ceive data paths will be retransmitted. In Minimum Mode, the Loopback Test Mode cannot be accessed. The IMR+ device will return to normal opera- tion when the TEST pin is again driven LOW. Am79C981 17306B-11 ...
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... TXP– Note 2 Note 1 RCV 100 Filter Transformer DO+ DO– Note 1 DI+ DI– CI+ CI– 40.2 40.2 40.2 40.2 0.1 F 0.1 F Optional ANLG GND Figure 7b. Typical AUI Port Components Am79C981 Filter & Transformer Module RJ45 Connector 1:1 TD+ 3 TD– 6 1:1 RD+ 1 RD– 2 17306B-12 Pulse AUI Connector ...
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... DAT and JAM are required for most applications. For more information, refer to AMD’s IEEE 802.3 Repeater Technical Manual (PID# 17314A). DAT CS JAM HIMIB C/D CRS CRS STR STR SCLK SCLK X1 D [7–0] RD ACK WR COL RDY RST INT CK Am79C981 Expansion Bus IMR+ REQ 17306B-14 ...
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... < V & (Note (Note Am79C981 AMD ) . . . . . . . . . . . . . . . . Min Max Unit –0.5 0.8 V 2 – 0.4 V 2.4 – V – –0.5 1 ...
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... Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz Sinusoid 5 MHz <f< 10 MHz (Note (Note (Note (Note 1) (Note MHz MHz MHz X1 Am79C981 Min Max Unit –500 +500 A 10 – –3.0 AV –1 –3.1 +3.1 V 300 520 mV –520 –300 mV ...
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... X1 rising edge to DAT/JAM not driven X1HDZ PRELIMINARY Test Conditions C = 100 100 100 100 100 100 100 100 pF L Am79C981 AMD Min Max Unit 49.995 50.005 – – 150 – – – ...
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... Test Conditions |V | > ASQ IN (Note > ASQ (Note > ASQ (Note > ASQ IN (Note > THS (Note 7) Am79C981 Min Max Unit 10 – – – – ns 200 – 100 ns 50 – – ns – ...
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... IMR+ chip; the remainder is dissipated externally in the twisted pair load and cable. PRELIMINARY PWODI PWOCI (min) will maintain internal RXD carrier sense on; pulse wider than t cable, an additional 28 mA (max Am79C981 AMD (max) will turn internal DI carrier sense on. (max) will turn internal PWKDI (max) will turn internal CI carrier sense on. ...
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... May Change from Don’t Care Any Change Permitted Does Not Apply X1H X1L t X1F Clock Timing Am79C981 OUTPUTS Will Be Steady Will Be Changing from Will Be Changing from Changing State Unknown Center Line is High Impedance “Off” State ...
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... IMR+ device clock phase relationships. SCLK t SCLKH SI/TEST SO t SODLY PRELIMINARY t RSTHLD t t RST or t PRST Reset Timing t t SCLK SCLKF t SCLKL t t SISET SIHLD t t TESTSET TESTHLD t SODLY Management Port Clock Timing Am79C981 AMD RSTSET 17306B-16 t SCLKR 17306B-19 1–101 ...
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... REQ t CASET ACK COL DAT JAM Note: *Externally generated (Figure 4) signal illustrates internal IMR+ chip clock phase relationships. 1–102 PRELIMINARY t t DJSET DJHOLD IN Expansion Port Input Timing t X1HRH t CASET t CAHOLD t t X1HDR X1HDZ OUT Expansion Port Output Timing Am79C981 17306B-20 17306B-21 ...
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... IMR+ chip clock phase relationships. Test RST X1 STR SI, Don’t Care SCLK PRELIMINARY t X1HRH t CASET t CAHOLD Expansion Port Collision Timing t MHSET t MHHLD To Enter Minimum Mode t t X1HSTH X1HSTL t t SCLKSET SCLKHLD Minimum Mode Am79C981 AMD IN 17306B-22 17306B-23 Don’t Care 17306B-24 1–103 ...
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... D0+ D0– DO+/– DI+/– V ASQ t PWKDI t PWODI 1–104 PRELIMINARY DOTR DOTF AUI DO Timing Diagram t DOETD 40 mV 100 mV max. 80-Bit Times AUI Port DO ETD Waveform AUI Receive Timing Diagram Am79C981 1 0 ETD t DOETD 17306B- 17306B-26 t PWKDI 17306B-27 ...
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... SWITCHING WAVEFORMS CI+/– V ASQ t PWOCI TXTD TXD+ TXP+ TXD– TXP– PRELIMINARY t PWKCI AUI Collision Timing Diagram TXTR XTXTF t TXTD TP Ports Output Timing Diagram Am79C981 AMD t PWKCI 17306B- ETD t TXETD 17306B-29 1–105 ...
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... AMD SWITCHING WAVEFORMS t PWPLP TXD+ TXP+ TXD– TXP– t PWLP V TSQ+ RXD+/– V TSQ– t PWKRD 1–106 PRELIMINARY t PWPLP t PERLP TP Idle Link Test Pulse t PWKRD TP Receive Timing Diagram Am79C981 17306B-30 t PWKRD V THS+ V THS– 17306B-31 ...
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... Includes Test Jig Capacitance AV SS 17306B-32 AUI DO Switching Test Circuit DV DD 294 Test Point 294 100 17306B-33 TXD Switching Test Circuit DV DD 715 Test Point 715 100 17306B-34 TXP Outputs Test Circuit Am79C981 AMD Test Point 1–107 ...
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... Integrated resistors, transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes. Transmit and receive filters and transformers. Transmit and receive common mode chokes. Transmit and receive filters and transformers, transmit common mode chokes. Am79C981 ...
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... Transmit Collision is indicated by the presence of a nominal 10 MHz signal on the CI+/- pins while the AUI port is transmitting on the DO+/- pins 10BASE-T port, Transmit Collision occurs when incoming data ap- pears on the RXD+/- pins while the 10BASE-T port is transmitting on the TXD+/- and TXP+/- pins. Am79C981 1–109 ...
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... Am79C981 ...