am79c981 Advanced Micro Devices, am79c981 Datasheet - Page 9

• Manufacturer Part Number: am79c981
• Description: Integrated Multiport Repeater Plus? Imr+? ??9
• Manufacturer: Advanced Micro Devices

FUNCTIONAL DESCRIPTION
The Am79C981 Integrated Multiport Repeater Plus de-
vice is a single chip implementation of an IEEE
802.3/Ethernet repeater (or hub). In addition to the eight
integral 10BASE-T ports plus one AUI port comprising
the basic repeater, the IMR+ chip also provides the
hooks necessary for complex network management
and diagnostics. The IMR+ device is also expandable,
enabling the implementation of high port count repeat-
ers based on several IMR+ devices.
The IMR+ device interfaces directly with AMD’s
Am79C987 Hardware Implemented Management Infor-
mation Base (HIMIB) device to allow a fully managed
multiport repeater to be implemented as specified by the
Layer Management for 10 Mb/s Baseband Repeaters
Standard. When the IMR+ and HIMIB devices are used
as a chip set, the HIMIB device maintains complete re-
peater and per port statistics which can be accessed on
demand by a microprocessor through a simple 8-bit par-
allel port.
The IMR+ chip complies with the full set of repeater ba-
sic functions as defined in section 9 of ISO 8802.3
(ANSI/IEEE 802.3c). These functions are summarized
below.
Repeater Function
If any single network port senses the start of a valid
packet on its receive lines, then the IMR+ device will re-
transmit the received data to all other enabled network
ports. The repeated data will also be presented on the
DAT line to facilitate multiple-IMR+ device repeater
applications.
Signal Regeneration
When re-transmitting a packet, the IMR+ device en-
sures that the outgoing packet complies with the 802.3
specification in terms of preamble structure, voltage am-
plitude, and timing characteristics. Specifically, data
packets repeated by the IMR+ chip will contain a mini-
mum of 56 preamble bits before the Start of Frame De-
limiter. In addition, the voltage amplitude of the repeated
packet waveform will be restored to levels specified in
the 802.3 specification. Finally, signal symmetry is re-
stored to data packets repeated by the IMR+ device,
removing jitter and distortion caused by the network
cabling.
Jabber Lockup Protection
The IMR+ chip implements a built-in jabber protection
scheme to ensure that the network is not disabled due to
transmission of excessively long data packets. This pro-
tection scheme will automatically interrupt the transmit-
ter circuits of the IMR+ device for 96-bit times if the IMR+
device has been transmitting continuously for more than
65,536-bit times. This is referred to as MAU Jabber
Lockup Protection (MJLP). The MJLP status for the
PRELIMINARY
Am79C981
IMR+ chip can be read through the Management Port
using the Get MJLP Status command (M bit returned).
Collision Handling
The IMR+ chip will detect and respond to collision condi-
tions as specified in 802.3. A multiple-IMR+ device re-
peater implementation also complies with the 802.3
specification due to the inter-IMR+ chip status commu-
nication provided by the expansion port. Specifically, a
repeater based on one or more IMR+ devices will han-
dle the transmit collision and one-port-left collision con-
ditions correctly as specified in Section 9 of the 802.3
specification.
Fragment Extension
If the total packet length received by the IMR+ device is
less than 96 bits, including preamble, the IMR+ chip will
extend the repeated packet length to 96 bits by append-
ing a Jam sequence to the original fragment.
Auto Partitioning/Reconnection
Any of the integral TP ports and AUI port can be parti-
tioned under excessive duration or frequency of colli-
sion conditions. Once partitioned, the IMR+ device will
continue to transmit data packets to a partitioned port,
but will not respond (as a repeater) to activity on the par-
titioned port’s receiver. The IMR+ chip will monitor the
port and reconnect it once certain criteria indicating port
‘wellness’ are met. The criteria for reconnection are
specified by the 802.3 standard. In addition to the stan-
dard reconnection algorithm, the IMR+ device imple-
ments an alternative reconnection algorithm which
provides a more robust partitioning function for the TP
ports and/or the AUI port. Each TP port and the AUI port
are partitioned and/or reconnected separately and inde-
pendently of other network ports.
Either one of the following conditions occuring on any
enabled IMR+ device network port will cause the port to
partition:
a. A collision condition exists continuously for a time
b. A collision condition occurs during each of 32 con-
Once a network port is partitioned, the IMR+ device will
reconnect that port if the following is met:
a. Standard reconnection algorithm—A data packet
b. Alternate reconnection algorithm—A data packet
between 1024- to 2048-bit times (AUI port—SQE
signal active; TP port—simultaneous transmit and
receive)
secutive attempts to transmit to that port.
longer than 512-bit times (nominal) is transmitted or
received by the partitioned port without a collision.
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
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