am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 127

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

CSR46: Transmit Poll Time Counter
Bit
31-16 RES
15-0
CSR47: Transmit Polling Interval
Bit
31-16 RES
15-0 TXPOLLINT
TXPOLL
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Transmit Poll Time Counter. This
counter is incremented by the
Am79C972 controller microcode
and is used to trigger the transmit
descriptor ring polling operation
of the Am79C972 controller.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Transmit Polling Interval. This
register contains the time that the
Am79C972 controller will wait be-
tween successive polling opera-
tions. The TXPOLLINT value is
expressed as the two’s comple-
ment of the desired interval,
where each bit of TXPOLLINT
represents 1 clock period of time.
TXPOLLINT[3:0]
(TXPOLLINT[16] is implied to be
a one, so TXPOLLINT[15] is sig-
nificant and does not represent
the sign of the two’s complement
TXPOLLINT value.)
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
CLK = 33 MHz). The TXPOL-
LINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR47 af-
ter H_RESET or S_RESET.
If the user desires to program a
value for POLLINT other than the
default, then the correct proce-
dure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
Description
Description
(1.966
are
ms
ignored.
when
Am79C972
CSR48: Receive Poll Time Counter
Bit
31-16 RES
15-0
CSR49: Receive Polling Interval
Bit
31-16 RES
15-0
RXPOLLINT Receive Polling Interval. This reg-
RXPOLL
Name
Name
Reserved locations. Written as
Reserved locations. Written as
user must set STOP (CSR0, bit
2). Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
overwritten with the desired user
value.
If the user does not use the stan-
dard
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead, chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR47 as
part of the alternative initialization
sequence.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
Receive Poll Time Counter. This
counter is incremented by the
Am79C972 controller microcode
and is used to trigger the receive
descriptor ring polling operation
of the Am79C972 controller.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
ister contains the time that the
Am79C972 controller will wait be-
tween successive polling opera-
tions. The RXPOLLINT value is
expressed as the two’s comple-
Description
Description
initialization
procedure
127