am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 104

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

10
9
8-7
104
MENDECL
LRT/TSEL
PORTSEL
TSEL
[1:0]
LRT
MENDEC Loopback Mode. See
the description of the LOOP bit
in CSR15.
Read/write
when STOP or SPND bits are
set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT = “1", the internal twisted
pair
reduced by 4.5 dB below the
standard
(approximately 3/5) and the
unsquelch threshold for the RXD
circuit will be 180-312 mV peak.
When LRT = “0", the unsquelch
threshold for the RXD circuit will
be
value, 300-520 mV peak.
In either case, the RXD circuit
post squelch threshold will be
one half of the unsquelch thresh-
old.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write
when STOP or SPND bits are
set. Cleared by RESET.
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO- yield “zero” dif-
ferential to operate transformer
coupled loads (Ethernet 2 and
802.3). When TSEL = 1, the DO+
idles at a higher value with
respect to DO-, yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected. Not available under
Auto-Select Mode.
Read/write
when STOP or SPND bits are
set. Cleared by RESET.
Port Select bits allow for software
controlled selection of the net-
work medium. PORTSEL active
only when Media-Select Bit set
to 0 in ISACSR2.
Read/write
when STOP or SPND bits are
set. Cleared by RESET.
the
receive
standard 10BASE-T
10BASE-T
accessible
accessible
accessible
accessible
thresholds
value
only
only
only
only
Am79C961A
are
*Refer to the section on General Purpose Serial Interface for
detailed information on accessing GPSI.
6
5
4
3
DXMTFCS
PORTSEL[1:0]
FCOLL
DRTY
INTL
0 0
0 1
1 0
1 1
The network port configuration
are as follows:
Internal
description of LOOP, CSR15.2.
Read/write
when STOP bit is set.
Disable Retry. When DRTY =
“1", PCnet-ISA II controller will
attempt only one transmission. If
DRTY = “0", PCnet-ISA II con-
troller will attempt to transmit 16
times before signaling a retry
error.
Read/write
when STOP or SPND bits are
set.
Force Collision. This bit allows
the collision logic to be tested.
PCnet-ISA II controller must be
in internal loopback for FCOLL
to be valid. If FCOLL = “1", a col-
lision will be forced during loop-
back transmission attempts; a
Retry Error will ultimately result.
If FCOLL = “0", the Force Colli-
sion logic will be disabled.
Read/write
when STOP or SPND bits are
set.
Disable Transmit CRC (FCS).
When DXMTFCS = “0", the
transmitter will generate and
append a FCS to the transmitted
frame. When DXMTFCS = “1",
the FCS logic is allocated to the
receiver and no FCS is generat-
ed or sent with the transmitted
frame.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set, no
FCS will be generated. If both
DXMTFCS is set and ADD_FCS
is clear for a particular frame, no
FCS
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
will
Loopback.
Network Port
be
accessible
accessible
accessible
10BASE-T
Reserved
GPSI*
AUI
generated. If
See the
only
only
only