am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 110

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

.
9-8 XMTFW[1:0]
110
RCVFW[1:0]
XMTFW[1:0]
XMTSP[1:0]
00
01
10
11
00
01
10
11
00
01
11-10XMTSP[1:0]Transmit Start
Point. XMTSP controls the point
at which preamble transmission
attempts commence in relation
to the number of bytes written to
the transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmis-
sion will start regardless of the
value in XMTSP. XMTSP is
given a value of 10b (64 bytes)
after RESET. Regardless of
XMTSP, the FIFO will not inter-
nally over-write its data until at
least 64 bytes (or the entire
frame if <64 bytes) have been
transmitted onto the network.
This ensures that for collisions
within the slot time window,
transmit data need not be
re-written to the transmit FIFO,
and retries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP or SPND bits
are set.
Transmit
XMTFW specifies the point at
which transmit DMA stops,
based upon the number of write
cycles that could be performed
to the transmit FIFO without
FIFO overflow. Transmit DMA is
allowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after
hardware RESET. Read/write
accessible only when STOP or
SPND bits are set.
Bytes Received
Bytes Written
FIFO
Write Cycles
Reserved
112
16
32
64
16
64
16
4
8
Watermark.
Am79C961A
7-0
CSR82: Bus Activity Timer
Bit
15-0 DMABAT
DMABR
XMTFW[1:0]
Name
10
11
DMA Burst Register. This reg-
ister contains the maximum
to system memory that the Bus
Interface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number of transfers during
zero will be interpreted as one
transfer.
BURST register. If DMAPLUS
(CSR4.14) is set, the DMA
Burst Register is disabled.
When the Bus Activity Timer
register (CSR82: DMABAT) is
enabled, the PCnet-ISA II con-
troller will relinquish the bus
when either the time specified
in DMABAT has elapsed or the
number of transfers specified
in DMABR have occurred or no
more pending operation left to
be performed.
Read/write
when STOP or SPND bits are
set.
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA II con-
troller will take up on the system
bus during FIFO data transfers
in each bus mastership period.
The DMABAT starts counting
upon receipt of DACK from the
host system. The DMABAT Reg-
ister does not limit the number of
transfers
transfers.
A value of zero will limit the PC-
net-ISA II controller to one bus
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a res-
olution of 100 ns. For instance, a
value of 51 s would be pro-
grammed with a value of 510.
When the TIMER bit in CSR4 is
set, DMABAT is enabled and
must be initialized by the user.
allowable number of transfers
Descriptor transfers. A value of
value of 16 is loaded in the
Description
During
during
Write Cycles
accessible
Reserved
32
RESET
Descriptor
only
a