am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 54

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

MULT (bit 11)
Multiple Match
This bit reflects the result of a “Find” operation. This bit
has meaning only if the FOUND bit is set. If this bit is set,
it indicates that more than one entry in the CAM matches
the value in the node processor comparand register.
This bit is cleared as a result of a “Skip” or
“Invalidate” operation.
ERROR (bit 10)
Error
This bit indicates that an improper operation was
attempted. This bit will be set for the following condtions:
If an attempt is made to issue the “Read CAM”
instruction while the EMPTY bit is set.
If the “Invalidate” or “Skip” instructions are issued and
the FOUND bit is not set.
If the Node Processor command operation is ignored
due to Receive Bus address match operation.
EMPTY (bit 9)
CAM EMPTY
This bit reflects the state of the CAM array. This bit
will be set if all entries in the CAM have their VALID
bits reset. EMPTY bit will be reset after write
CAM command.
BISTDONE (bit 8)
BIST Complete
This bit reflects the state of the built-in self test (BIST).
This bit will be cleared after reset, while BIST is running
and after an instruction is issued to the command
register. It will be set once BIST is complete.
Revision Number
Bits 7, 6 and 5 provide a three-bit binary value that
indicates the revision number of the Address Filter.
54
AMD
P R E L I M I N A R Y
SUPERNET 3
Reserved (bits 4:0)
Reserved
These bits are reserved for future use. These bits should
always be written with zeroes to ensure compatibility
with future revisions of the AF. These bits will always
read back as zeroes.
BIST Signature Register (AFBIST)
This is a 16-bit register that may be read and written by
the node processor. After the initiation of BIST, this
register will hold the signature resulting from the
execution of built-in self test when the BISTDONE bit is
set in the status register.
Comparand Registers (AFCOMP2:0)
The comparand registers are 16-bit registers that may
be read and written by the node processor. AFCOMP0
corresponds to bits 15:0 of the CAM entry. AFCOMP1
corresponds to bits 31:16 of the CAM entry. AFCOMP2
corresponds to bits 47:32 of the CAM entry. This register
will be cleared (filled with zeroes) on a reset and will
retain its data after each time it is written until the next
reset. This register will be updated with the contents of
the first matching entry in the CAM if a “Read CAM”
instruction is issued to the command register while the
FOUND bit is set.
FC
DA (47:32) DA (31:16)
AFCOMP2 AFCOMP1 AFCOMP0
DA (15:0)
SA