am79c875 Advanced Micro Devices, am79c875 Datasheet - Page 26

• Manufacturer Part Number: am79c875
• Description: Netphy ?lp Low Power Quad 10/100-tx/fx Ethernet Transceiver
• Manufacturer: Advanced Micro Devices

MII Management Control Register (Register 0)
26
Reg
0
0
0
0
0
0
0
0
0
0
6:0
Bit
15
14
13
12
10
11
9
8
7
Auto-Neg Enable
Auto-Negotiation
Speed Select
Duplex Mode
Collision Test
Power Down
Loopback
Reserved
Restart
Isolate
Name
Reset
Table 7.
Description
1 = PHY reset.
0 = Normal operation.
This bit is self-clearing.
1 = Enable loopback mode. This will loopback TXD to RXD,
thus it will ignore all the activity on the cable media.
0 = Disable loopback mode. Normal operation.
1 = 100 Mbps.
0 = 10 Mbps.
1 = Enable Auto-Negotiation process (overrides 0.13 and 0.8).
0 = Disable Auto-Negotiation process.
1 = Power down. The NetPHY™ 4LP device will shut off all
blocks except for MDIO/MDC interface.
0 = Normal operation.
1 = Electrically isolate the PHY from MII. However, PHY is still
able to respond to MDC/MDIO.
0 = Normal operation.
1 = Restart Auto-Negotiation process.
0 = Normal operation.
1 = Full duplex.
0 = Half duplex.
Auto-Negotiation enabled: This bit is writable but will be
ignored.
Auto-Negotiation disabled: This pin is reset read value of
DPLX.
1 = Enable collision test, which issues the COL signal in
response to the assertion of TX_EN signal. Collision test is
enabled regardless of the duplex mode.
0 = disable COL test.
Write as 0, ignore on read.
MII Management Control Register (Register 0)
Am79C875
RW/SC
RW/SC
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
FORCE100
ANEGA pin
DPLX pin
Default
Set by
Set by
Set by
pin
0
0
0
0
0
0
0