am79c875 Advanced Micro Devices, am79c875 Datasheet - Page 31

• Manufacturer Part Number: am79c875
• Description: Netphy ?lp Low Power Quad 10/100-tx/fx Ethernet Transceiver
• Manufacturer: Advanced Micro Devices

Miscellaneous Features Register (Register 16)
Interrupt Control/Status Register (Register 17)
Reg
Reg
16
16
16
16
16
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
12:4
3:0
Bit
15
14
13
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
Link_Not_OK_ IE
A_Neg_Comp Int
Link_Not_OK Int
ANeg_Comp_IE
PD_Fault_Int
INTR_LEVL
Page_Rx_Int
Page_Rx_IE
PD_Fault_IE
R_Fault_Int
LP_Ack_Int
LP_Ack_IE
R_Fault_IE
Reserved
Reserved
Reserved
Jabber_Int
Jabber_IE
Rx_Er_Int
Rx_Er_IE
TXJAM
Name
Name
Table 16. Miscellaneous Features Register (Register 16)
Table 17.
Description
Write as 0; 1 = factory use only.
1 = INT is forced to 1 to signal an interrupt.
0 = INT is forced to 0 to signal an interrupt.
1 = Force CIM to send jam pattern.
0 = Normal operation mode.
Write as 0, ignore when read.
Ignore when read.
Description
Jabber Interrupt Enable.
Receive Error Interrupt Enable.
Page Received Interrupt Enable.
Parallel Detection Fault Interrupt Enable.
Link Partner Acknowledge Interrupt Enable.
Link Status Not OK Interrupt Enable.
Remote Fault Interrupt Enable.
Auto-Negotiation Complete Interrupt Enable.
This bit is set when a jabber event is detected.
This bit is set when RX_ER transitions high.
This bit is set when a new page is received from link partner during
Auto-Negotiation.
This bit is set when parallel detect fault is detected.
This bit is set when the FLP with acknowledge bit set is received.
This bit is set when link status switches from OK status to Non-OK
status (Fail or Ready).
This bit is set when remote fault is detected.
This bit is set when Auto-Negotiation is complete.
Interrupt Control/Status Register (Register 17)
Am79C875
Read/
Write
RW
RW
RW
RO
RO
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
RC
RC
RC
RC
RC
RC
RC
RC
Default
00000
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31