am79c30a Advanced Micro Devices, am79c30a Datasheet - Page 46

• Manufacturer Part Number: am79c30a
• Description: Digital Subscriber Controller ?dsc ?circuit
• Manufacturer: Advanced Micro Devices

D-Channel Status Register 2 — (DSR2) — Read Only
DSR2 has the format illustrated in Table 46.
Note:
*Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H.
The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hard-
ware reset or Idle mode).
46
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
Generate Interrupt
Yes, if DMR3 bit 2 = 1 When last byte of a received packet is read from the
Yes, if DMR1 bit 3 = 1 When DCRB contains one or more bytes of data
Yes, if DMR3 bit 6 = 1 When two outstanding packets are received and not
Yes, if DMR3 bit 4 = 1 When the last byte of a transmit packet is transferred from
Yes, if DMR3 bit 5 = 1 When the DCTB is available to be loaded with a data byte When the DCTB is full
No
No
Yes, if EFCR bit 1 = 1
Logical 1
Last byte of received packet
Receive byte available
Receive packet lost
Last byte transmitted
Transmit buffer available
Mark idle detected (15 or more contiguous 1s)
Flag idle detected (more than two contiguous flags) Flag idle not detected
Start of second received packet in FIFO
Bit Set
DCRB
serviced, and a third packet is received
the DCTB
When 15 contiguous one bits have been detected in the
incoming D channel
When more than two contiguous flags are detected on the
incoming D channels, not including a closing flag
When start of second packet is in the receive FIFO
Table 46. D-Channel Status Register 2
Am79C30A/32A Data Sheet
Table 47. DSR2 Interrupts
Logical 0 (Default Value)
Not last byte of received packet
Receive byte not available
Receive packet not lost
Last byte not transmitted
Transmit buffer not available*
Mark idle not detected
Second packet not yet in FIFO
Bit Reset
When the microprocessor reads the
DSR2
When the microprocessor reads
DSR2
When the microprocessor reads
DSR2
When the first zero bit is detected
on the incoming D channel
When a non-flag character is
detected on the incoming D channel
When second receive packet is not
present
When DCRB is empty