m36p0r9060n0 Numonyx, m36p0r9060n0 Datasheet - Page 10

• Manufacturer Part Number: m36p0r9060n0
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Mux I/o, Multi-chip Package
• Manufacturer: Numonyx

2 Signal descriptions
2.5
2.6
2.7
2.8
2.9
2.10
10/23
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KM096AA datasheet for the PSRAM
and to the M58PRxxxJN datasheet for the Flash memory.
Flash Chip Enable input (E
The Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory. When Chip Enable is Low, V
device is in active mode. When Chip Enable is at V
outputs are high impedance and the power consumption is reduced to the standby level.
It is not allowed to have E
component can be enabled at a time.
Flash Output Enable inputs (G
The Output Enable input controls the data outputs during Flash memory Bus Read
operations.
Flash Write Enable (W
The Write Enable input controls the Bus Write operation of the Flash memory Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Flash Write Protect (WP
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V
Down blocks cannot be changed. When Write Protect is at High, V
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M58PRxxxJN datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the Flash memories. When Reset is at V
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
value of I
reset. When Reset is at V
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
RPH
(refer to the M58PRxxxJN datasheet).
DD2
. After Reset all blocks are in the Locked state and the Configuration Register is
IL
F
, Lock-Down is enabled and the protection status of the Locked-
F
)
IH
at V
, the device is in normal operation. Exiting Reset mode the
IL
F
and E
)
F
)
DD2
P
F
at V
. Refer to the M58PRxxxJN datasheet, for the
)
IL
F
)
at the same time. Only one memory
IH
the Flash memory are deselected, the
IL
, and Reset is High, V
IH
, Lock-Down is disabled
M36P0R9060N0
IH
IL
, the
, the