m36p0r9060n0 Numonyx, m36p0r9060n0 Datasheet - Page 9

• Manufacturer Part Number: m36p0r9060n0
• Description: 512 Mbit X16, Multiple Bank, Multi-level, Burst Flash Memory 64 Mbit Burst Psram, 1.8v Supply, Mux I/o, Multi-chip Package
• Manufacturer: Numonyx

M36P0R9060N0
2
2.1
2.2
2.3
2.4
Signal descriptions
See
connected to this device.
Address Inputs (ADQ0-ADQ15 and A16-A24)
Addresses A0-A21 are common inputs for the Flash memory and PSRAM components.
Addresses A22 and A24 are inputs for the Flash memory component only.
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
Data Input/Output (ADQ0-ADQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KM096AA for the PSRAM and M58PRxxxJN for the
Flash memory.
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KM096AA for the PSRAM and M58PRxxxJN for the Flash
memory.
Figure 1., Logic diagram
and
Table 1., Signal
names, for a brief overview of the signals
2 Signal descriptions
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