tfra08c13 ETC-unknow, tfra08c13 Datasheet - Page 35

• Manufacturer Part Number: tfra08c13
• Description: Tfra08c13 Octal T1/e1 Framer
• Manufacturer: ETC-unknow

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Frame Formats
Transparent Framing Format
The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system
interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (FRM_PR43 bits
2—0 must be set to 000) and either transparent framing mode 1 or transparent framing mode 2 is enabled
(FRM_PR26 bit 3 or bit 4 must be set to 1).
In transparent mode 1 or mode 2, the transmit framer extracts from the receive system data bit 8 of time slot 1 and
inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot
1 are ignored by the transmit framer. The receive framer will extract the F-bit (or 193rd bit) of the receive line data
and insert it into bit 7 of time slot 1 of the system data; the other bits of time slot 1 are set to 0.
Frame integrity is maintained in both the transmit and receive framer sections.
In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than
bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer
will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data.
In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of
receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will insert
the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The remaining
bits in time slot 1 are set to 0.
TIME SLOT 1
0
0
TIME SLOT 2 TIME SLOT 3
F BIT
(STUFF TIME SLOT)
0
(continued)
TIME SLOT 1 TIME SLOT 2
0
SYSTEM INTERFACE CONTROL REGISTER BITS[2:0] = 000.
0
0
Figure 8. T1 Transparent Frame Structure
0
F BIT
SYSTEM FRAME SYNC MASK REGISTER FRM_PR26 BIT 3 OR BIT 4 = 1.
FRAME INTEGRITY IS MAINTAINED WITH F BIT AND THE SYSTEM PAYLOAD.
TIME SLOT 31 TIME SLOT 32
TIME SLOT 24
TFRA08C13 OCTAL T1/E1 Framer
32 TIME-SLOT CHI FRAME
TRAMSMIT FRAMER’S
193-bit FRAME
DS1 = 125 s
5-5989(F).b
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