txc-03108 TranSwitch Corporation, txc-03108 Datasheet - Page 8

• Manufacturer Part Number: txc-03108
• Description: 8-channel Framer
• Manufacturer: TranSwitch Corporation

Ed. 2, May 2001
T1Fx8
TXC-03108
TXC-03108-MA
The following features are only selectable for the eight framers as a group:
• Transmission/Data Modes (“off line” framing) or MVIP/H-MVIP/H.100 Modes as system interfaces
• Serial port to read/write controls up to eight line interface transceivers ("Host Mode") with broad-
• Selection of one of eight DS1 line interfaces (receive line, receive terminal, or transmit) to monitor
• Microprocessor global reset, masks, polling registers, interrupt polarity and latch edge control
• Motorola split address/data with LDS option or Intel split address/data
• Global alarm Indications with separate channel pointers for DS1 alarms, FDL activity, and loop-
• Global interrupt mask bits
• Interrupt on alarms
• Hardware interrupt polarity selection
• Two reference clock outputs at 8 kHz or 1544 kHz with freeze on LOS and with the 8 kHz synchro-
• IEEE 1149.1 boundary scan
• Ability to tristate all outputs for in-circuit testing with a single control lead.
• Synchronization start position is programmable to any receive or transmit bit position on the sys-
• External shadow register clock input
1.544 Mbit/s Data
2.048 Mbit/s MVIP
8 Mbit/s H-MVIP
1.544 Mbit/s Transmission:
cast option
clock, frame pulse and data
backs
nized to the frame pulse as an option.
tem side to any one of 256 positions
Positive edge
Negative edge
Both edges
Proprietary TranSwitch Corporation Information for use Solely by its Customers
3 ms multiframe refresh rate
Defined signaling highway format to carry signaling, AIS and RAI
Receive system frame and clock out when slip buffers bypassed
Receive system frame and clock in when slip buffers enabled
125 s refresh rate
ABCD signaling nibble per DS0 channel on signaling highway
Receive system frame and clock out when slip buffers bypassed
Receive system frame and clock in when slip buffers enabled
125 s refresh rate
32 time slots
Slip buffers enabled (receive system clock and frame are inputs)
Four DS1 formats byte-interleaved on two signaling and two data Highways
125 s refresh rate
Slip buffers enabled (receive system clock and frame are inputs)
H.100 compliant option for frame pulse width
TECHNICAL OVERVIEW
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