am85c30 Advanced Micro Devices, am85c30 Datasheet - Page 17

• Manufacturer Part Number: am85c30
• Description: Enhanced Serial Communications Controller
• Manufacturer: Advanced Micro Devices

Interrupt on First Character or Special Condition and In-
terrupt on Special Condition Only are typically used with
the Block Transfer mode. A Special Receive Condition
is one of the following: receiver overrun, framing error in
asynchronous mode, end-of-frame in SDLC mode, and
optionally, a parity error. The Special Receive Condition
interrupt is different from an ordinary Receive Character
Available interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In Interrupt on
First Receive Character, an interrupt can occur from
Special Receive Conditions any time after the first
Receive Character Interrupt.
The main function of the External/Status interrupt is to
monitor the signal transitions of the CTS, DCD, and
SYNC pins; however, an External/Status interrupt is
also caused by a Transmit Underrun condition, a zero
count in the baud rate generator, the detection of a
Break (asynchronous mode), Abort (SDLC mode), or
EOP (SDLC Loop mode) sequence in the data stream.
The interrupt caused by the Abort or EOP has a special
feature allowing the ESCC to interrupt when the Abort or
EOP sequence is detected or terminated. This feature
facilitates the proper termination of the current
PROGRAMMING INFORMATION
Each channel has fifteen Write registers that are indi-
vidually programmed from the system bus to configure
the functional personality of each channel. Each chan-
nel also has eight Read registers from which the system
can read Status, Baud rate, or Interrupt information.
On the Am85C30, only four data registers (Read and
Write for Channels A and B) are directly selected by a
High on the D/C input and the appropriate levels on the
RD, WR, and A/B pins. All other registers are addressed
indirectly by the content of Write Register 0 in conjunc-
tion with a Low on the D/C input and the appropriate lev-
els on the RD, WR, and A/B pins. If bit D
bits 5 and 6 are 0, then bits 0, 1, and 2 address the higher
registers 8 through 15. If bits 4, 5, and 6 contain a differ-
ent code, bits 0, 1, and 2 address the lower registers 0
through 7 as shown in Table 2.
3
in WR0 is 1 and
Am85C30
message, correct initialization of the next message, and
the accurate timing of the Abort condition in external
logic in SDLC mode. In SDLC Loop mode, this feature
allows secondary stations to recognize the wishes of the
primary station to regain control of the loop during a poll
sequence.
CPU/DMA Block Transfer
The SCC provides a Block Transfer mode to accommo-
date CPU block transfer functions and DMA controllers.
The Block Transfer mode uses the WAIT/REQUEST
output in conjunction with the Wait/Request bits in WR1.
The WAIT/REQUEST output can be defined under soft-
ware control as a WAIT line in the CPU Block Transfer
mode or as a REQUEST line in the DMA Block Transfer
mode.
To a DMA controller, the ESCC REQUEST output indi-
cates that the ESCC is ready to transfer data to or from
memory. To the CPU, the WAIT line indicates that the
SCC is not ready to transfer data, thereby requesting
that the CPU extend the I/O cycle. The DTR/REQUEST
can be used as the transmit request line, thus allowing
full-duplex operation under DMA control.
Writing to or reading from any register except RR0,
WR0, and the data registers thus involves two
operations:
First, write the appropriate code into WR0, then follow
this by a Write or Read operation on the register thus
specified. Bits 0 through 4 in WR0 are automatically
cleared after this operation, so that WR0 then points to
WR0 or RR0 again.
Channel A/Channel B selection is made by the A/B input
(High = A, Low = B).
The system program first issues a series of commands
to initialize the basic mode of operation. This is followed
by other commands to qualify conditions within the se-
lected mode. For example, the asynchronous mode,
character length, clock rate, number of stop bits, even or
odd parity might be set first. Then the interrupt mode
would be set and, finally, receiver or transmitter enable.
AMD
17