k4d263238k Samsung Semiconductor, Inc., k4d263238k Datasheet
k4d263238k
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k4d263238k Summary of contents
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... K4D263238K 128Mbit GDDR SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4D263238K Revision History Revision Month Year 1.0 January 2007 1.1 July 2007 - Release revision 1.0 SPEC - Corrected Package Outline - Revised comment about voltage of power up sequence - Revised ICC2P current to 20mA - 2/19 - 128M GDDR SDRAM History Rev. 1.1 July 2007 ...
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... K4D263238K-VC50 K4D263238K-GC is the Leaded package part number. GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D263238K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized 1,048,576 words by 32 bits, fabricated with SAMSUNG extremely high performance up to 2.0GB/s/chip. ...
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... K4D263238K PIN CONFIGURATION (Top View DQS0 DM0 VSSQ C DQ4 VDDQ NC D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ G DQ19 DQ18 VDDQ H DQS2 DM2 NC DQ21 DQ20 VDDQ J DQ22 DQ23 VDDQ K CAS WE VDD L RAS BA0 N NOTE: 1. RFU1 is reserved for A12 2 ...
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... K4D263238K INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type *1 Input CK, CK CKE Input CS Input RAS Input CAS Input WE Input DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply REF *1 : The timing reference point for the differential clocking is the cross point of CK and CK ...
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... K4D263238K BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D263238K FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or with - Apply VDDQ before or with - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal ...
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... K4D263238K MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D263238K EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extend mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... K4D263238K ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... K4D263238K DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I P CC2 in Power-down mode Precharge Standby Current I N CC2 in Non Power-down mode Active Standby Current I P CC3 power-down mode Active Standby Current in ...
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... K4D263238K AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Output CAPACITANCE (V =2.5V Parameter ...
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... K4D263238K AC CHARACTERISTICS Parameter CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...
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... K4D263238K Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... AC CHARACTERISTICS (II) K4D263238K-VC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 K4D263238K-VC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 * 200/166MHz are supported in K4D263238K-VC40 * 166MHz is supported in K4D263238K-VC50 -40 Symbol Min Max tRC 48 - tRFC 56 - tRAS 32 100K tRCDRD 16 - tRCDWR 8 ...
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... K4D263238K Simplified Timing(2) @ BL=4, CL CK, CK BA[1:0] BAa BAa Ra Ra A8/AP ADDR Ca Ra (A0~A7, A9~,A11) WE DQS Da0 Da1 Da2 Da3 DQ DM ACTIVEA WRITEA COMMAND tRCD tRAS tRC Normal Write Burst (@ BL= BAa BAa BAb PRECH ACTIVEA ACTIVEB tRP tRRD ...
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... K4D263238K PACKAGE DIMENSIONS (144-Ball FBGA) 0.10 Max 0.45 ± 0.05 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0 ± 0.05 0.40 Max <Bottom View> - 17/19 - 128M GDDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 Unit : mm Rev. 1.1 July 2007 ...
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... K4D263238K IBIS :I/V Characteristics for Input and Output Buffers Pulldown Current(mA) Voltage(V) Minimum 0 0.1 0.2 0.3 15.28 0.4 20.56 0.5 0.6 30.36 0.7 34.88 0.8 38.96 0.9 42.64 1 45.76 1.1 1.2 50.48 1.3 52.04 1.4 53.24 1.5 54.16 1.6 1.7 55.32 1.8 55.76 1.9 56.16 2 56.48 2.1 2.2 57.08 2.3 57.36 2.4 57.64 2.5 57.84 2.6 58.08 2.7 58.28 Maximum 0 0 4.2 5.24 9.92 11.36 17.24 23.12 25.6 28.76 34.24 39.48 44.64 49.48 53.92 48.4 57.92 61.56 64.72 67.28 69.44 54.8 71.2 72.52 73.48 74.28 74.92 56.8 75.4 75.84 76.24 76.56 76.8 77.12 77.36 Full Strength Driver Characteristics - 18/19 - 128M GDDR SDRAM Pullup Current(mA) Minimum Maximum 0 1.84 -2.88 -7.44 -11.84 -16 -20.04 -23.92 -27.52 -30.8 -33.88 -36.6 -39 -41.08 -42.84 -44.24 -45.44 -46.44 -47.28 -47.96 -48.68 -49.28 -49.84 -50.36 -50.48 -50.52 -50.55 -50.58 Rev. 1.1 July 2007 0 2.44 -2.88 -8.16 -13.16 -18.24 -23.08 -27.84 -32.4 -36.84 -41.04 -45.04 -48.84 -52.48 -55.76 -58.84 -61.56 -64.04 -66.16 -68.04 -69.64 -71.04 -72.24 -73.36 -74.24 -75.08 -75.84 -76.56 ...
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... K4D263238K Pulldown Current(mA) Voltage(V) Minimum 0 0.1 0.2 0.3 12.24 0.4 16.44 0.5 20.36 0.6 24.08 0.7 27.36 0.8 30.48 0.9 33.12 1 35.32 1.1 37.08 1.2 1.3 39.44 1.4 40.16 1.5 40.72 1.6 41.12 1.7 41.52 1.8 41.84 1.9 42.08 2 42.32 2.1 42.56 2.2 42.76 2.3 42.96 2.4 43.16 2.5 43.32 2.6 43.52 2.7 43.68 Weak Strength Driver Characteristics Maximum 0 0 3.48 4.32 7.96 9.2 14 18.76 23.2 27.6 31.8 35.68 39.36 42.6 45.6 38.4 48.08 50.2 51.92 53.28 54.32 55.08 55.68 56.2 56.56 56.92 57.24 57.44 57.72 57.92 58.12 58.32 - 19/19 - 128M GDDR SDRAM Pullup Current(mA) Minimum Maximum 0 0.96 -2.92 -6.56 -10.12 -13.64 -16.8 -19.88 -22.72 -25.32 -27.64 -29.72 -31.52 -33.04 -34.28 -35.36 -36.2 -36.92 -37.6 -38.12 -38.6 -39.08 -39.48 -39.92 -40.12 -40.15 -40.18 -40.2 Rev. 1.1 July 2007 0 -2.68 -7.4 -11.96 -16.4 -20.68 -24.84 -28.88 -32.8 -36.48 -40.08 -43.44 -46.44 -49.36 -51.96 -54.4 -56.48 -58.36 -60 -61.48 -62.72 -63.8 -64.8 -65.64 -66.4 -67.12 -67.72 -68.32 ...
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... K4D263238K Pulldown Current(mA) Voltage(V) Minimum 0 0.1 0.2 0.3 10.28 0.4 13.72 0.5 16.84 0.6 19.84 0.7 22.48 0.8 24.88 0.9 1 28.44 1.1 1.2 30.52 1.3 31.24 1.4 1.5 32.12 1.6 32.44 1.7 32.68 1.8 32.92 1.9 33.16 2 33.28 2.1 33.48 2.2 33.64 2.3 2.4 33.92 2.5 34.12 2.6 34.24 2.7 34.36 Maximum 0 0 3.08 0.84 6.76 4.84 8.56 12.32 15.92 19.36 22.64 25.72 26.8 28.56 31.16 29.6 33.44 35.36 36.96 31.8 38.16 39.12 39.84 40.4 40.84 41.2 41.44 41.72 41.88 33.8 42.08 42.24 42.44 42.56 42.68 Matched Strength Driver Characteristics - 20/19 - 128M GDDR SDRAM Pullup Current(mA) Minimum Maximum 0 0.24 -2.76 -5.68 -8.44 -11.08 -13.56 -15.8 -17.96 -19.88 -21.56 -23.04 -24.36 -25.36 -26.24 -26.96 -27.56 -28.04 -28.56 -28.92 -29.28 -29.6 -29.96 -30.24 -30.34 -30.38 -30.41 -30.42 Rev. 1.1 July 2007 0 -2.36 -5.88 -9.36 -12.8 -16.16 -19.24 -22.32 -25.16 -27.92 -30.52 -32.92 -35.12 -37.12 -38.88 -40.52 -41.96 -43.12 -44.24 -45.12 -45.96 -46.6 -47.28 -47.84 -48.36 -48.84 -49.28 -49.68 ...