k4d261638k Samsung Semiconductor, Inc., k4d261638k Datasheet - Page 13

• Manufacturer Part Number: k4d261638k
• Description: 128mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

DECOUPLING CAPACITANCE GUIDE LINE
9.6 AC CHARACTERISTICS
9.5 CAPACITANCE
K4D261638K
Recommended decoupling capacitance added to power line at board.
1. V
2. V
Decoupling Capacitance between V
Decoupling Capacitance between V
CK cycle time
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV
- tQHmin = tHP-X where
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
that data strobe are coincidentally valid.
the clock duty cycle applied to the device is better than 45/55%
Input capacitance( CK, CK )
Input capacitance(A
Input capacitance( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ
Input capacitance(DM0 ~ DM3)
DD
SS
and V
and V
Parameter
SSQ
DDQ
pins are separated each other. All V
pins are separated each other. All V
Parameter
0
~A
Parameter
11
, BA
0
~BA
CL=2
CL=3
DD
DDQ
1
)
and V
and V
0
SS
~DQ
SSQ
15
tWPREH
tWPRES
tDQSCK
Symbol
tDQSQ
tWPST
tRPRE
tDQSS
tDQSH
tRPST
tDQSL
)
tCH
tDH
tQH
tCK
tCK
tAC
tDS
tHP
SS
tCL
DD
tIS
tIH
pins are connected in chip. All V
pins are connected in chip. All V
- 13 /19 -
tHP-0.4
tCHmin
tCLmin
Symbol
0.45
0.45
0.85
0.35
Min
-0.6
-0.6
C
7.5
4.0
0.9
0.4
0.4
0.4
0.4
0.9
0.9
0.4
0.4
C
C
C
C
or
0
-
OUT
IN1
IN2
IN3
IN4
-40
Symbol
C
C
DC1
DC2
Max
0.55
0.55
1.15
0.4
0.6
0.6
1.1
0.6
0.6
0.6
0.6
10
10
-
-
-
-
-
-
-
-
Min
1.0
1.0
1.0
1.0
1.0
SSQ
DDQ
tHP-0.45
tCHmin
tCLmin
0.45
0.45
0.45
0.45
Min
-0.7
-0.7
7.5
5.0
0.9
0.4
0.8
0.3
0.4
0.4
0.4
1.0
1.0
pins are connected in chip.
or
0
-
pins are connected in chip.
0.1 + 0.01
0.1 + 0.01
128M GDDR SDRAM
Value
-50
(VDD=2.5V, TA= 25°C, f=1MHz)
Max
0.55
0.55
0.45
0.6
Max
0.7
0.7
1.1
1.2
0.6
0.6
0.6
10
10
5.0
4.0
4.0
6.5
6.5
-
-
-
-
-
-
-
-
Rev. 1.3 July 2007
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
uF
uF
Unit
pF
pF
pF
pF
pF
Note
1
1
1